timer_example.c

TI DM648 TIMER配置源代码,可以下接下到板子上,非常不错

/* =============================================================================
 * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006, 2007
 *
 *   Use of this software is controlled by the terms and conditions found
 *   in the license agreement under which this software has been supplied.
 * ==========================================================================*/

/** ===========================================================================
 *  @file Timer_example.c
 *
 *  @path $(CSLPATH)\example\dm648\timer\src
 *
 *  @desc Example for the usage of timer register layer macros
 *
 *  ============================================================================
 *   @n Target Platform: EVM
 *  ============================================================================
 *  @n <b> Example Description </b>
 *  @n The example illustartes the usage of timer register layer macros.
 *    1. This example configures the first instance of timer
 *       as Dual Unchain mode and as Watch dog timer
 *    2. The  timer status bit is read to determine the completion.
 *    3. The above said procedure is followed for all the modes of the timer
 *       (i.e.  dual 32 bit timer(unchained) and watchdog).
 *  ============================================================================
 *      
 *   <b> Procedure to run the example </b>
 *   @verbatim
 *      1. Configure the CCS setup to work with the emulator being used
 *      2. Please refer CCS manual for setup configuration and loading 
 *         proper GEL file
 *      3. Launch CCS window
 *      4. Open project Timer_example.pjt
 *      5. Build the project and load the .out file of the project.
 *          
 *   @endverbatim
 *   
 * =============================================================================
 */ 

/** ============================================================================
 *  Revision History
 *  =============== 
 *  8-May-2007 PSK  File Created.
 * ============================================================================= 
 */

#include <stdio.h>
#include <soc.h>
#include <cslr_tmr.h>
#include <cslr_psc.h>

/* Locals & Forwards */
void timer0DualUnchainDemo(void);
void timer0WdtDemo(void);
void enableTimer0(void);

/* Pointer to register overlay structure for PSC */
CSL_PscRegsOvly pscRegs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;
/* Pointer to register overlay structure for TIMER0*/
CSL_TmrRegsOvly tmrRegs = (CSL_TmrRegsOvly)CSL_TMR_0_REGS;


/*
 * =============================================================================
 *   @func   main
 *
 *   @desc
 *     This is the main routine for the file.
 *
 * =============================================================================
 */
void main (
    void
)
{   
    enableTimer0();    
    timer0DualUnchainDemo();
    timer0WdtDemo();

    printf(">>>>>> Timer Example completed  <<<<<<<< \n");
}

/*
 * =============================================================================
 *   @func  timer0DualUnchainDemo
 *  
 *   @arg
 *      NONE
 *
 *   @desc
 *     This is the example code for Timer register layer macro usage to 
 *     configure timer in Dual Unchained Mode.
 *
 *   @return
 *      NONE
 *
 * =============================================================================
 */
void timer0DualUnchainDemo (
    void
)
{
    Uint32 tmpReg;

    
    printf("Running Timer0(low) in DUAL UNCHAINED ....\n");
    
    /* Load the Period register's */
    tmrRegs->PRD12 = 100;
    
    /* Load the counter register's */
    tmrRegs->TIM12 = 0;
   
	tmpReg = tmrRegs->TCR;

    /* Setup the TCR register  configurations */
    
    /* The Clock source is set to internal */
    CSL_FINST(tmpReg, TMR_TCR_CLKSRC12, INTERNAL);
    /* The Pulse width is 1 timer clock cycle */
    CSL_FINST(tmpReg, TMR_TCR_PWID, ONE_CLKCYCLE);
    /* Mode for Timer Output is pulse mode */
    CSL_FINST(tmpReg, TMR_TCR_CP, PULSE);
    /* Noninverted timer input drives the timer*/
    CSL_FINST(tmpReg, TMR_TCR_INVINP, UNINVERTED);
    /* The timer output is inverted */
    CSL_FINST(tmpReg, TMR_TCR_INVOUTP, UNINVERTED);

	tmrRegs->TCR = tmpReg;
     
    /* set the operation mode */
    /* Set the timer operating mode to Dual Unchain */
    CSL_FINST(tmrRegs->TGCR, TMR_TGCR_TIMMODE, DUAL_UNCHAIN);
    /* Put the timer in Reset */
	CSL_FINST(tmrRegs->TGCR, TMR_TGCR_TIM12RS, RESET_ON);
	/* Take the timer out of reset */ 
	CSL_FINST(tmrRegs->TGCR, TMR_TGCR_TIM12RS, RESET_OFF);
	/* Set the enable mode to continuos mode */
    CSL_FINST(tmrRegs->TCR, TMR_TCR_ENAMODE12, CONTINUOUS);

    /* Read the Timer Status bit */
    while (1) {
        if (CSL_FEXT(tmrRegs->TCR, TMR_TCR_TSTAT) == 1)
            break;
    }
      
    /**************************************************************/
    /* Put the timer in Reset */
	CSL_FINST(tmrRegs->TGCR, TMR_TGCR_TIM12RS, RESET_ON);
    
    printf("Example for Timer0(Low) completed\n");

}

/*
 * =============================================================================
 *   @func  tmrWdtModeDemo
 *  
 *   @arg
 *      NONE
 *
 *   @desc
 *      This demonstrates the Setting of timer to watchdog mode with INTC.
 *
 *   @return
 *      NONE
 *
 * =============================================================================
 */
void timer0WdtDemo (
    void
)
{
    Uint32 tmpReg;
    
    tmrRegs->PRD12 = 100;
    tmrRegs->PRD34 = 0;
    
    /* Load the counter register's */
    tmrRegs->TIM12 = 0;
    tmrRegs->TIM34 = 0;
    
	tmpReg = tmrRegs->TCR;

    /* Setup the TCR register  configurations */
    CSL_FINST(tmpReg, TMR_TCR_CLKSRC12, INTERNAL);
    /* The Pulse width is 3 timer clock cycle */
    CSL_FINST(tmpReg, TMR_TCR_PWID, THREE_CLKCYCLE);
    /* Mode for Timer Output is pulse mode */    
    CSL_FINST(tmpReg, TMR_TCR_CP, PULSE);
    /* Noninverted timer input drives the timer*/    
    CSL_FINST(tmpReg, TMR_TCR_INVINP, UNINVERTED);
    /* The timer output is inverted */    
    CSL_FINST(tmpReg, TMR_TCR_INVOUTP, UNINVERTED);   
    
	tmrRegs->TCR = tmpReg;
	
    /* set the operation mode */
    /* Set the timer operating mode to Watchdog timer */        
	CSL_FINST(tmrRegs->TGCR, TMR_TGCR_TIMMODE, WDTMR);

	tmpReg = tmrRegs->TGCR;
 	/* Take the timer out of reset */ 
    CSL_FINST(tmpReg, TMR_TGCR_TIM12RS, RESET_OFF);	
 	/* Take the timer out of reset */ 
    CSL_FINST(tmpReg, TMR_TGCR_TIM34RS, RESET_OFF);
    tmrRegs->TGCR = tmpReg;
    
    /* Enable the watchdog timer */
    CSL_FINST(tmrRegs->WDTCR, TMR_WDTCR_WDEN, ENABLE);
    
    tmpReg = 0;
    tmpReg = tmrRegs->TCR;
	/* Set the enable mode to continuos mode */
    CSL_FINST(tmpReg, TMR_TCR_ENAMODE12, CONTINUOUS);
    CSL_FINST(tmpReg, TMR_TCR_ENAMODE34, CONTINUOUS);
    tmrRegs->TCR = tmpReg;

    /* Write the watchdog timer service key bits */
    CSL_FINST(tmrRegs->WDTCR, TMR_WDTCR_WDKEY, CMD1);
    CSL_FINST(tmrRegs->WDTCR, TMR_WDTCR_WDKEY, CMD2);

    /* Read the Watchdog timer flag bit */
    while (1) {
        if (CSL_FEXT(tmrRegs->WDTCR, TMR_WDTCR_WDFLAG) == 1)
            break;
    }
      
    /**************************************************************/

    printf("Example for Timer Watch dog mode completed\n");

}

/*
 * ============================================================================
 *   @func   enableTimer0
 *
 *   @desc
 *     This function enables the powerSaver for Timer module instance 0.
 *
 *  @arg  
 *      None
 *
 *  @return
 *      None
 * ============================================================================
*/

void enableTimer0(void)
{
    /* enable TIMER0 LPSC*/
    pscRegs->MDCTL[CSL_PSC_TIMER0] = CSL_FMKT(PSC_MDCTL_NEXT, ENABLE) | 
                                   CSL_FMKT(PSC_MDCTL_LRST, DEASSERT);
    
    pscRegs->PTCMD = CSL_FMKT(PSC_PTCMD_GO0, SET);
    
    while (CSL_FEXT(pscRegs->MDSTAT[CSL_PSC_TIMER0], PSC_MDSTAT_STATE)
          != CSL_PSC_MDSTAT_STATE_ENABLE);   
}