pllc_example.c

TI DM648 PLL配置源代码,可以下接下到板子上,非常不错

/*  ============================================================================
 *   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006, 2007
 *
 *   Use of this software is controlled by the terms and conditions found in the
 *   license agreement under which this software has been supplied.
 *  ============================================================================
 */

/** ============================================================================
 *   @file  Pllc_example.c
 *
 *   @path $(CSLPATH)\example\dm648\pllc\src
 *
 *   @desc  Example of PLLC module Register layer CSL
 *
 *
 *  ============================================================================
 *   @n Target Platform: EVM
 *  ============================================================================
 *   @n <b> Example Description </b>
 *   @n The example shows PLLC module register layer CSL usage
 *      This example configures PLL0
 *  ============================================================================
 *
 *   <b> Procedure to run the example </b>
 *   @verbatim
 *      1. Configure the CCS setup to work with the emulator being used.
 *         Refer CCS manual for setup configuration.
 *      2. Load required GEL file depending on the board used.
 *      3. Launch CCS window.
 *      4. Open project pllc_example.pjt.
 *      5. Build the project and load the .out file of the project.
 *
 *   @endverbatim
 *
 *
 *  ============================================================================
 */

/*  ============================================================================
 *  Revision History
 *  ===============
 *  22-Sep-2005 Tej File Modified.
 *  19-Dec-2005 SD  Modified according to the review comments 
 *  06-Feb-2006 SD  Modified according to the spec changes
 *
 *  ============================================================================
 */

#include <stdio.h>
#include <cslr_pllc0.h>
#include <soc.h>

#define CSL_PLLC0_PLLCTL_PLLENSRC_REGBIT  (0x00000000u)
#define CSL_PLLC0_PLLCTL_PLLRST_NO        (0x00000000u)
#define CSL_PLLC0_PLLCTL_PLLRST_YES       (0x00000001u) 

void setupPll0(int pll_multiplier);

/*
 * =============================================================================
 *   @func   sw_wait
 *
 *   @desc
 *     This is the delay routine.
 *
 * =============================================================================
 */
void sw_wait (int delay) 
{
    volatile int i;
    for( i = 0; i < delay; i++ ) {
    }
}

/*
 * =============================================================================
 *   @func   main
 *
 *   @desc
 *     This is the main routine which calls example routine.
 *
 * =============================================================================
 */

void main()
{
  printf("Configure PLL0 with register layer macros\n");

  setupPll0(20);
}

/*
 * =============================================================================
 *   @func   setupPll0
 *
 *   @desc
 *     This is the actual routine which configures PLL0.
 *
 * =============================================================================
 */
void setupPll0(int pll_multiplier)
{
    CSL_Pllc0RegsOvly pllcRegs;

    /* Pointer to register overlay structure */
    pllcRegs = ((CSL_Pllc0RegsOvly)CSL_PLLC_0_REGS);    

    printf("Please wait DM648 System PLL Initialisation is in Progress.....\n");     

    /* Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled through MMR */ 
    CSL_FINST(pllcRegs->PLLCTL, PLLC0_PLLCTL_PLLENSRC, REGBIT);

    /*Set PLL BYPASS MODE */ 
    CSL_FINST(pllcRegs->PLLCTL, PLLC0_PLLCTL_PLLEN, BYPASS);

    /*wait for some cycles to allow PLLEN mux switches properly to bypass clock*/ 
    sw_wait(150);

    /* Reset the PLL */ 
    CSL_FINST(pllcRegs->PLLCTL, PLLC0_PLLCTL_PLLRST, YES);

    /*PLL stabilisation time*/ 
    sw_wait(1500);

    /*Program PREDIV Reg, POSTDIV register and OSCDIV1 Reg 
    1.predvien_pi is set to '1'  
    2.prediv_ratio_lock_pi is set to '1', RATIO field of PREDIV is locked 
    3.Set the PLLM Register 
    4.Dont program POSTDIV Register 
    */ 

    /* Set PLL Multiplier */
    pllcRegs->PLLM = pll_multiplier;

    /*wait for PLL to Reset properly=>PLL reset Time*/ 
    sw_wait(128);

    /*Bring PLL out of Reset*/ 
    CSL_FINST(pllcRegs->PLLCTL, PLLC0_PLLCTL_PLLRST, NO);     

    /*Wait for PLL to LOCK atleast 2000 MXI clock or Reference clock cycles*/ 
    sw_wait(2000);

    /*Enable the PLL Bit of PLLCTL*/ 
    CSL_FINST(pllcRegs->PLLCTL, PLLC0_PLLCTL_PLLEN, PLL);      

    printf("PLL0 has been configured\n");       
}