tlv2548sweep_m.asm

TLV2544/48 Interface routine

*=============================================================================*
*All software and related documentation is provided "AS IS" and without 		*
*warranty or support of any kind and Texas Instruments expressly disclaims 	*
*all other warranties,express or implied, including, but not limited to, the  *
*implied warranties of merchantability and fitness for a particular purpose.  *
*Under no circumstances shall Texas Instruments be liable for any incidental, *
*special or consequential damages that result from the use or inability to 	*
*use the software or related documentation, even if Texas Instruments has 	   *
*been advised of the liability.															   *
*																									   *
*Unless otherwise stated, software written and copyrighted by Texas 			   *
*Instruments is distributed as "freeware". You may use and modify this 		   *
*software without any charge or restriction. You may distribute to others,	   *
*as long as the original author is acknowledged.										*
*=============================================================================*
**************************************************************************
* TITLE         : TLV2544/48 Interface routine                           *
* FILE          : tlv2548Sweep_m.ASM                                     *
* FUNCTION      : MAIN                                                   *
* PROTOTYPE     : void SweepMode ()                                      *
* CALLS         : N/A                                                    *
* PRECONDITION  : N/A                                                    *
* POSTCONDITION : N/A                                                    *
* DESCRIPTION   :
*This routine is written to demonstrate sweep mode of the TLV2548 ADC.   * 
*The program expects the calling program to store the configuration word *
*in Config_Command, the channel Conversion Command in _Conv_Command, the *
*memory location to store sample in _StoreAt, and number of samples to   *
*gather in _NumToStore.   The code starts of by setting the DSP, CPLD,	 *
*and McBSP0 registers for this interface.  The ADC is then configured,   *
*and conversions triggered.  Once the FIFO is filled, the DSP sits idle  *
*until an interrupt is received from the ADC.  When an interrupt is 	    *
*received the DSP jumps to Interrupt Service Routine(ISR). The DSP reads *
*the data out of the FIFO, stores the data in respective data table, 	 *
*checks to see if it's collected enough samples, then returns to main 	 *
*program.  A FIFO level of 2 is assumed, so only one two data tables 	 *
*are initialized.                 *												    *
* AUTHOR        : AAP Application Group, L. Philipose, Dallas, Tx	       *
*                 CREATED 2000(C) BY TEXAS INSTRUMENTS INCORPORATED.     *
* REFERENCE     : TMS320C54x User's Guide, TI 1997                       *
*               : Data Aquisation Circuits, TI 1999                      *
**************************************************************************

 
         .title   "TLV2544/48 ADC"
         .mmregs
         .width   80
         .length  55 
         		         
    .sect ".vectors"
    .copy "C5402vec.asm"                                    
    
    .sect ".data"
    .include	regs.h

**Global Variables**
 .global _SweepMode
 .global _StoreAt
 .global _NumToStore
 .global _Config_Command
 .global _Conv_Command
 .global _CLKGDV

**Variables**
AD_DP       		.usect ".varibl", 0  	;Data page label for variables.
_StoreAt	    		.usect ".varibl", 1  	;Address to begin Storing Samples
_NumToStore   		.usect ".varibl", 1  	;Total Number of Samples to Collect
_Config_Command   .usect ".varibl", 1  	;Configuration Word
_Conv_Command	  	.usect ".varibl", 1  	;Command word to ADC
_CLKGDV  	    	.usect ".varibl", 1  	;Variable used to set CLKX/R on McBSP0

ADWORD      		.usect ".varibl", 1   	;Converted Data stored t
Temp      			.usect ".varibl", 1    	;
FIFO_LEVEL  		.usect ".varibl", 1    ;FIFO set to Trigger Interrupt at this Level
EndOfTable    		.usect ".varibl", 1  	;End of Table
Next_Table    		.usect ".varibl", 1  	;Next Table to store Sample
Quit_Now	   		.usect ".varibl", 1  	;Next Table to store Sample


Input_CH_0			.set 00000h
Input_CH_1			.set 01000h
Input_CH_2			.set 02000h
Input_CH_3			.set 03000h
Input_CH_4			.set 04000h
Input_CH_5			.set 05000h
Input_CH_6			.set 06000h
Input_CH_7			.set 07000h
SW_PWR_DWN			.set 08000h
Read_CFR				.set 09000h
Write_CFR			.set 0A000h
Self_Test_Half		.set 0B000h
Self_Test_MINUS	.set 0C000h
Self_Test_PLUS		.set 0D000h
FIFO_Read			.set 0E000h

    
    .sect ".text" 

_SweepMode: 
_MAIN:
start:
 
***Intialize DSP***

 	DP=#0;									;Memory Mapped Registers in Data Page 0
	CLKMD = #4007h							;Set c5402 DSP clock to 100MHz.
    
  	INTM=#1									;Disable maskable interrupts. 
  	CPL=#0									;Using DP for relative addressing mode
	SXM=#0    			   				;No Sign Extension
	PMST = #00F8h;   						;Re-map Interrupt Vector Table to 0x0080h in Program Memory
 	IMR  = #0100h;    					;Enabled Interrupt #3     	
	IFR  = #0FFFFh;   					;Clear all Pending Interrupts	
	
	SWWSR = #2000h;      				;Need Wait-State of at least 2.                      
	
	DP=#AD_DP								;Change Data Page to where Variables are stored.
		
	@Temp=#0088h							;Enable INT3 From Daugthercard.
  	port(DSP_CPLD_CNTL1) =@Temp 		;
    
   @Temp=#0001h
	port(DSP_CPLD_CNTL2) =@Temp  		;Select daughter board as source for McBSP0

	call McBSP0_init						;Set McBSP0 registers
     
	INTM=#0									;enable global interrupts
	
	DP=#AD_DP								;
	XF = 0									;SET CSz. ADC Chip Select is held low throughout this program.
	A=@_StoreAt
	AR7=A								   	;Address to begin storing Samples at.
												
 	@Quit_Now=#0                     ;0->Continue sampling
												;1->Return to C 
 	
	call FIFO_LEVEL_SET	 				;Determine FIFO Trigger Level	 
	@Next_Table=#0

*Configure the ADC *						;Transmit Word Store in Accum. A.  Receive Word Stored in Accum. B
	A=@_Config_Command					;Configuration Word, Choose external SCLK, and Single shot mode.
	call ADC_Write_Read					;Write and Read from McBSP0.  Write the Configuration Data to 
												;ADC, and read out receiver data register.  Receiver data is stored 
												;in Accumulator B.  In this case we don't care what was received.


	
Wait: 

	A=@FIFO_LEVEL
	BRC = A
	NOP	
	NOP
	blockrepeat(continueCYCLE-1)
	
	A=@_Conv_Command
	call ADC_Write_Read 
    repeat(#6)       
	nop	            
continueCYCLE:	     						;end_block repeat   
	
    
	idle(#1) 								;DSP power-down until INT3 occurs


	RETURN 									;Sweep Sequence Completed Return to calling Function


**Intialize McBSP0 for 16-bit transfers, SCLK derived from CPU clock**
**Set SCLK frequency using @_CLKGDV 								**
McBSP0_init:	
    
	mmr(McBSP0_SPSA) = #SPCR1       	;Reset McBSP0 Receiver 
	A=mmr(McBSP0_SPSD)	            ;
	A = #0FFFEh & A  						;RRST*=0
	mmr(McBSP0_SPSD) =A
	
	mmr(McBSP0_SPSA) = #SPCR2       	;Reset McBSP0 Receiver  
	A=mmr(McBSP0_SPSD)				
	A= A & #0FF7Fh							;FRST*=0
	A= A & #0FFBFh                  	;GRST*=0
	A= A & #0FFFEh                  	;XRST*=0	
	
	A=A|#0200h								;enable free running mode
	mmr(McBSP0_SPSD) = A  				;			
	
	mmr(McBSP0_SPSA) = #PCR         	;FSXM & CLKXM output pin driven 
	mmr(McBSP0_SPSD) = #0A00h       	;by Sample Rate Generator
												;FSRM & CLKRM input pins
												;driven by external source
     	
	
	mmr(McBSP0_SPSA) = #RCR1        	;
	mmr(McBSP0_SPSD) = #0040h       	;One 16-bit Word per frame  
	

	mmr(McBSP0_SPSA) = #RCR2        	;One 16-bit Word per frame
	mmr(McBSP0_SPSD) = #0041h       	;one bit receive bit data delay 
   	
									
	mmr(McBSP0_SPSA) = #XCR1        
	mmr(McBSP0_SPSD) = #0040h       	;One 16-bit Word per frame   

   	mmr(McBSP0_SPSA) = #XCR2      ;One 16-bit Word per frame
	mmr(McBSP0_SPSD) = #0041h       	;one bit receive bit data delay 
		
	mmr(McBSP0_SPSA) = #SRGR1       	;FS width=one clock 

	A= #0100h                			;
	NOP
	NOP
	B=@_CLKGDV              			;CLKGDV=9->10Mhz
	NOP
	NOP
	A=A|B           						;CLKGDV=4->20Mhz
	mmr(McBSP0_SPSD) = A       		;SRG clock divider=9 (CPU Clock /1+CLKGDC)=10Mhz

	mmr(McBSP0_SPSA) = #SRGR2       	;SRG clock derived from CPU clock 
	mmr(McBSP0_SPSD) = #2018h       	;FSX due to transfer DXR->XSR

	
	mmr(McBSP0_SPSA) = #SPCR2       	;  
	A=mmr(McBSP0_SPSD) 
	A= A | #00080h							;FRST*=1
	A= A | #0040h                   	;GRST*=1

    mmr(McBSP0_SPSD)  = A      		;Frame Generator and sample
    											;Sample-Rate generator enabled	
     
	
	A= A | #0001h                   	;XRST*=1	 
    mmr(McBSP0_SPSD)  = A      		;Transmitter enabled
    
    repeat(#6)                      ;wait for transmitter to become active
    NOP       
    
    mmr(McBSP0_SPSA) = #SPCR1   		;RRST*=1
	A= mmr(McBSP0_SPSD) 
	A= A | #0001h
	mmr(McBSP0_SPSD) = A					;Reciever enabled
	
	repeat(#6)								;wait for receiver to become active
    NOP  
    
	RETURN	

	
	

**Function Write to Transmitter and Read from Receiver of McBSP0**
**Data to be written out must be stored in Accum. A, 				 **
**Data received in stored in Accumulator B							 **

ADC_Write_Read:							;input in A
	PUSH (AR2)								;Save Registers
	PUSH (AR1)
	PUSH (AR0)
Wait_On_Transmitter:   
	DP=#0
	mmr(McBSP0_SPSA) = #SPCR2       	;Check to see if tranmitter is ready to send 
	B=mmr(McBSP0_SPSD)        			;new data.
	
	B=B & #0002h;
	AR1=B
   	nop
	nop
	AR0=#2
	nop
	nop
	TC      = (AR0 == AR1)      
    if (NTC) goto Wait_On_Transmitter 	;If transmitter is full wait until it is not.
	AR2=#McBSP0_DXR1
	nop
   *AR2 = A										;Send out to ADC
	 
Wait_On_Receiver:
	DP=#0
	mmr(McBSP0_SPSA) = #SPCR1     		; 
	B=mmr(McBSP0_SPSD)         			;Check to see if Receiver is FULL with Data
	AR0=#2
	B=B & #0002h;
	AR1=B
	nop
	nop

	TC = (AR0 == AR1)      
   if (NTC) goto Wait_On_Receiver  		;If receiver is not ready with new data, then wait.
  	DP=#AD_DP		
	AR2=#McBSP0_DRR1 
	NOP
   B=*AR2 										;Read out ADC   
   AR0 =POP()
   AR1 =POP()
   AR2 =POP()
	RETURN

**Function determines the Level FIFO is set to trigger interrupt.**
**FIFO Level is saved in variable FIFO_Level **	
FIFO_LEVEL_SET:  
	
   A=@_Config_Command					;Load ADC configuration Word and determine
	A=A & #0003h							;FIFO Trigger Level
 	
 	@Temp=A
	TC=(@Temp == #0)						;If it set to FIFO level 7?
	if (NTC) goto NOT_FIFO__LEVEL_7
	A=#7	 	
 	@FIFO_LEVEL=A            
	
	goto FIFO_SET 	
NOT_FIFO__LEVEL_7:						;Not Level 7, if FIFO set to trigger when
	TC=(@Temp == #1)						;level 5 is filler?
	if (NTC) goto NOT_FIFO__LEVEL_5
	A=#5	 	
 	@FIFO_LEVEL=A
 	
 	goto FIFO_SET
NOT_FIFO__LEVEL_5:						;Not set to trigger at level 7 or 5.  Maybe 
												;Level 3?
	TC=(@Temp == #2)
	if (NTC) goto NOT_FIFO__LEVEL_3
	A=#3	 	
 	@FIFO_LEVEL=A  
 	
	goto FIFO_SET
NOT_FIFO__LEVEL_3:						;Not Set to Trigger at Level 7,5,3. Then has to be 1.
	A=#1	 									;FIFO has Two Levels 0,1.  When these levels are filled
 	@FIFO_LEVEL=A  						;TLV254x will generate an Interrupt.

FIFO_SET:

 	
     RETURN  

 
ISR_int03:

    DP  = #AD_DP
    A=@FIFO_LEVEL					   		;Load in Block Repeat Counter Register the number of
	BRC = A							   		;FIFO levels to Read.
	NOP	
	NOP

	blockrepeat(Readout_FIFO-1)
    repeat(#5)
	nop	

 	A=#FIFO_Read 							  	;Write Command FIFO Read.
  	call ADC_Write_Read  				  	;This prompts the ADC to shift 
												  	;FIFO contents out.
	   	
	TC      = (@Next_Table == #0)     	;Decide where to store FIFO Contents
   	if (TC) goto Table_0    			;Either in Table One or Table Two.
	TC      = (@Next_Table == #1)      	;This code is written for a FIFO trigger level set to 1.  
   	if (TC) goto Table_1     	
	goto Read_Next_FIFO   	
Table_0:   	
	*AR7+     = data(@ADWORD)     		;Point to first date location of the storage table	
	@Next_Table	=#1
	goto Read_Next_FIFO
Table_1:                          	
    *AR6+     = data(@ADWORD)     		;Point to first date location of the storage table	
    @Next_Table	=#0
	
Read_Next_FIFO:	
	nop
Readout_FIFO:  
    goto Continue              

Continue:	
	
    return_enable   

  .end