led8bit.fit.qmsg

MAXII_DEV_BOARD EPM240的开发板电路图。

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.505 ns register register " "Info: Estimated most critical path is register to register delay of 11.505 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkdiv\[10\] 1 REG LAB_X4_Y3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 5; REG Node = 'clkdiv\[10\]'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkdiv[10] } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.250 ns) + CELL(0.200 ns) 2.450 ns LessThan1~391 2 COMB LAB_X5_Y2 1 " "Info: 2: + IC(2.250 ns) + CELL(0.200 ns) = 2.450 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'LessThan1~391'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.450 ns" { clkdiv[10] LessThan1~391 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.740 ns) 3.630 ns LessThan1~392 3 COMB LAB_X5_Y2 1 " "Info: 3: + IC(0.440 ns) + CELL(0.740 ns) = 3.630 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'LessThan1~392'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.180 ns" { LessThan1~391 LessThan1~392 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.360 ns) + CELL(0.914 ns) 5.904 ns LessThan1~394 4 COMB LAB_X5_Y3 1 " "Info: 4: + IC(1.360 ns) + CELL(0.914 ns) = 5.904 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'LessThan1~394'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.274 ns" { LessThan1~392 LessThan1~394 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.941 ns) + CELL(0.914 ns) 8.759 ns LessThan1~395 5 COMB LAB_X7_Y4 1 " "Info: 5: + IC(1.941 ns) + CELL(0.914 ns) = 8.759 ns; Loc. = LAB_X7_Y4; Fanout = 1; COMB Node = 'LessThan1~395'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.855 ns" { LessThan1~394 LessThan1~395 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 139 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.155 ns) + CELL(0.591 ns) 11.505 ns buzzer~reg0 6 REG LAB_X7_Y3 2 " "Info: 6: + IC(2.155 ns) + CELL(0.591 ns) = 11.505 ns; Loc. = LAB_X7_Y3; Fanout = 2; REG Node = 'buzzer~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.746 ns" { LessThan1~395 buzzer~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 37 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.359 ns ( 29.20 % ) " "Info: Total cell delay = 3.359 ns ( 29.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.146 ns ( 70.80 % ) " "Info: Total interconnect delay = 8.146 ns ( 70.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.505 ns" { clkdiv[10] LessThan1~391 LessThan1~392 LessThan1~394 LessThan1~395 buzzer~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 " "Info: Average interconnect usage is 6% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "6 X0_Y0 X8_Y5 " "Info: Peak interconnect usage is 6% of the available device resources in the region that extends from location X0_Y0 to location X8_Y5" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "6 " "Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led7sel\[0\] GND " "Info: Pin led7sel\[0\] has GND driving its datain port" {  } { { "d:/program/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program/altera/72/quartus/bin/pin_planner.ppl" { led7sel[0] } } } { "d:/program/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "led7sel\[0\]" } } } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 24 -1 0 } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[0] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led7sel\[1\] GND " "Info: Pin led7sel\[1\] has GND driving its datain port" {  } { { "d:/program/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program/altera/72/quartus/bin/pin_planner.ppl" { led7sel[1] } } } { "d:/program/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "led7sel\[1\]" } } } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 24 -1 0 } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[1] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led7sel\[2\] GND " "Info: Pin led7sel\[2\] has GND driving its datain port" {  } { { "d:/program/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program/altera/72/quartus/bin/pin_planner.ppl" { led7sel[2] } } } { "d:/program/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "led7sel\[2\]" } } } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 24 -1 0 } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[2] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led7sel\[3\] GND " "Info: Pin led7sel\[3\] has GND driving its datain port" {  } { { "d:/program/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program/altera/72/quartus/bin/pin_planner.ppl" { led7sel[3] } } } { "d:/program/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "led7sel\[3\]" } } } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 24 -1 0 } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[3] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led7sel\[4\] GND " "Info: Pin led7sel\[4\] has GND driving its datain port" {  } { { "d:/program/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program/altera/72/quartus/bin/pin_planner.ppl" { led7sel[4] } } } { "d:/program/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "led7sel\[4\]" } } } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 24 -1 0 } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[4] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "led7sel\[5\] GND " "Info: Pin led7sel\[5\] has GND driving its datain port" {  } { { "d:/program/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/program/altera/72/quartus/bin/pin_planner.ppl" { led7sel[5] } } } { "d:/program/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "led7sel\[5\]" } } } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 24 -1 0 } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[5] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led7sel[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.fit.smsg " "Info: Generated suppressed messages file E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "167 " "Info: Allocated 167 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 28 22:38:12 2008 " "Info: Processing ended: Mon Apr 28 22:38:12 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}