prev_cmp_led8bit.tan.qmsg

MAXII_DEV_BOARD EPM240的开发板电路图。

{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[1\] led\[1\]~reg0 8.699 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[1\]\" through register \"led\[1\]~reg0\" is 8.699 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns led\[1\]~reg0 2 REG LC_X3_Y3_N0 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y3_N0; Fanout = 2; REG Node = 'led\[1\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk led[1]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[1]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[1]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.975 ns + Longest register pin " "Info: + Longest register to pin delay is 4.975 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led\[1\]~reg0 1 REG LC_X3_Y3_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y3_N0; Fanout = 2; REG Node = 'led\[1\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led[1]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.653 ns) + CELL(2.322 ns) 4.975 ns led\[1\] 2 PIN PIN_3 0 " "Info: 2: + IC(2.653 ns) + CELL(2.322 ns) = 4.975 ns; Loc. = PIN_3; Fanout = 0; PIN Node = 'led\[1\]'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.975 ns" { led[1]~reg0 led[1] } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.67 % ) " "Info: Total cell delay = 2.322 ns ( 46.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.653 ns ( 53.33 % ) " "Info: Total interconnect delay = 2.653 ns ( 53.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.975 ns" { led[1]~reg0 led[1] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "4.975 ns" { led[1]~reg0 {} led[1] {} } { 0.000ns 2.653ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[1]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[1]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.975 ns" { led[1]~reg0 led[1] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "4.975 ns" { led[1]~reg0 {} led[1] {} } { 0.000ns 2.653ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "led\[5\]~reg0 rst clk -2.990 ns register " "Info: th for register \"led\[5\]~reg0\" (data pin = \"rst\", clock pin = \"clk\") is -2.990 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns led\[5\]~reg0 2 REG LC_X6_Y4_N1 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N1; Fanout = 2; REG Node = 'led\[5\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk led[5]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[5]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[5]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.559 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.559 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_44 22 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_44; Fanout = 22; PIN Node = 'rst'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.623 ns) + CELL(0.804 ns) 6.559 ns led\[5\]~reg0 2 REG LC_X6_Y4_N1 2 " "Info: 2: + IC(4.623 ns) + CELL(0.804 ns) = 6.559 ns; Loc. = LC_X6_Y4_N1; Fanout = 2; REG Node = 'led\[5\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.427 ns" { rst led[5]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns ( 29.52 % ) " "Info: Total cell delay = 1.936 ns ( 29.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.623 ns ( 70.48 % ) " "Info: Total interconnect delay = 4.623 ns ( 70.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.559 ns" { rst led[5]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "6.559 ns" { rst {} rst~combout {} led[5]~reg0 {} } { 0.000ns 0.000ns 4.623ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[5]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[5]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.559 ns" { rst led[5]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "6.559 ns" { rst {} rst~combout {} led[5]~reg0 {} } { 0.000ns 0.000ns 4.623ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 28 22:36:46 2008 " "Info: Processing ended: Mon Apr 28 22:36:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}