prev_cmp_led8bit.tan.qmsg

MAXII_DEV_BOARD EPM240的开发板电路图。

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register clkdiv\[13\] register buzzer~reg0 78.875 ns " "Info: Slack time is 78.875 ns for clock \"clk\" between source register \"clkdiv\[13\]\" and destination register \"buzzer~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "86.6 MHz 11.547 ns " "Info: Fmax is 86.6 MHz (period= 11.547 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "89.713 ns + Largest register register " "Info: + Largest register to register requirement is 89.713 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "90.422 ns + " "Info: + Setup relationship between source and destination is 90.422 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 90.422 ns " "Info: + Latch edge is 90.422 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 90.422 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 90.422 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 90.422 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 90.422 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns buzzer~reg0 2 REG LC_X7_Y3_N2 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X7_Y3_N2; Fanout = 2; REG Node = 'buzzer~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk buzzer~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk buzzer~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} buzzer~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns clkdiv\[13\] 2 REG LC_X4_Y3_N6 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y3_N6; Fanout = 5; REG Node = 'clkdiv\[13\]'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk clkdiv[13] } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk clkdiv[13] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} clkdiv[13] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk buzzer~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} buzzer~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk clkdiv[13] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} clkdiv[13] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns - " "Info: - Micro setup delay of destination is 0.333 ns" {  } { { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk buzzer~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} buzzer~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk clkdiv[13] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} clkdiv[13] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.838 ns - Longest register register " "Info: - Longest register to register delay is 10.838 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkdiv\[13\] 1 REG LC_X4_Y3_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y3_N6; Fanout = 5; REG Node = 'clkdiv\[13\]'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkdiv[13] } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.050 ns) + CELL(0.740 ns) 2.790 ns LessThan0~570 2 COMB LC_X5_Y2_N7 1 " "Info: 2: + IC(2.050 ns) + CELL(0.740 ns) = 2.790 ns; Loc. = LC_X5_Y2_N7; Fanout = 1; COMB Node = 'LessThan0~570'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.790 ns" { clkdiv[13] LessThan0~570 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.740 ns) 4.238 ns LessThan1~392 3 COMB LC_X5_Y2_N5 1 " "Info: 3: + IC(0.708 ns) + CELL(0.740 ns) = 4.238 ns; Loc. = LC_X5_Y2_N5; Fanout = 1; COMB Node = 'LessThan1~392'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.448 ns" { LessThan0~570 LessThan1~392 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.732 ns) + CELL(0.200 ns) 6.170 ns LessThan1~394 4 COMB LC_X5_Y3_N8 1 " "Info: 4: + IC(1.732 ns) + CELL(0.200 ns) = 6.170 ns; Loc. = LC_X5_Y3_N8; Fanout = 1; COMB Node = 'LessThan1~394'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.932 ns" { LessThan1~392 LessThan1~394 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.173 ns) + CELL(0.200 ns) 8.543 ns LessThan1~395 5 COMB LC_X7_Y4_N5 1 " "Info: 5: + IC(2.173 ns) + CELL(0.200 ns) = 8.543 ns; Loc. = LC_X7_Y4_N5; Fanout = 1; COMB Node = 'LessThan1~395'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.373 ns" { LessThan1~394 LessThan1~395 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.704 ns) + CELL(0.591 ns) 10.838 ns buzzer~reg0 6 REG LC_X7_Y3_N2 2 " "Info: 6: + IC(1.704 ns) + CELL(0.591 ns) = 10.838 ns; Loc. = LC_X7_Y3_N2; Fanout = 2; REG Node = 'buzzer~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.295 ns" { LessThan1~395 buzzer~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.471 ns ( 22.80 % ) " "Info: Total cell delay = 2.471 ns ( 22.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.367 ns ( 77.20 % ) " "Info: Total interconnect delay = 8.367 ns ( 77.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.838 ns" { clkdiv[13] LessThan0~570 LessThan1~392 LessThan1~394 LessThan1~395 buzzer~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "10.838 ns" { clkdiv[13] {} LessThan0~570 {} LessThan1~392 {} LessThan1~394 {} LessThan1~395 {} buzzer~reg0 {} } { 0.000ns 2.050ns 0.708ns 1.732ns 2.173ns 1.704ns } { 0.000ns 0.740ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk buzzer~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} buzzer~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk clkdiv[13] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} clkdiv[13] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.838 ns" { clkdiv[13] LessThan0~570 LessThan1~392 LessThan1~394 LessThan1~395 buzzer~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "10.838 ns" { clkdiv[13] {} LessThan0~570 {} LessThan1~392 {} LessThan1~394 {} LessThan1~395 {} buzzer~reg0 {} } { 0.000ns 2.050ns 0.708ns 1.732ns 2.173ns 1.704ns } { 0.000ns 0.740ns 0.740ns 0.200ns 0.200ns 0.591ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register led\[3\]~reg0 register led\[4\]~reg0 1.645 ns " "Info: Minimum slack time is 1.645 ns for clock \"clk\" between source register \"led\[3\]~reg0\" and destination register \"led\[4\]~reg0\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.490 ns + Shortest register register " "Info: + Shortest register to register delay is 1.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led\[3\]~reg0 1 REG LC_X6_Y4_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y4_N3; Fanout = 2; REG Node = 'led\[3\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led[3]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.899 ns) + CELL(0.591 ns) 1.490 ns led\[4\]~reg0 2 REG LC_X6_Y4_N5 2 " "Info: 2: + IC(0.899 ns) + CELL(0.591 ns) = 1.490 ns; Loc. = LC_X6_Y4_N5; Fanout = 2; REG Node = 'led\[4\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { led[3]~reg0 led[4]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.591 ns ( 39.66 % ) " "Info: Total cell delay = 0.591 ns ( 39.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.899 ns ( 60.34 % ) " "Info: Total interconnect delay = 0.899 ns ( 60.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { led[3]~reg0 led[4]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "1.490 ns" { led[3]~reg0 {} led[4]~reg0 {} } { 0.000ns 0.899ns } { 0.000ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.155 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.155 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 90.422 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 90.422 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 90.422 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 90.422 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns led\[4\]~reg0 2 REG LC_X6_Y4_N5 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N5; Fanout = 2; REG Node = 'led\[4\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk led[4]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[4]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[4]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns led\[3\]~reg0 2 REG LC_X6_Y4_N3 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X6_Y4_N3; Fanout = 2; REG Node = 'led\[3\]~reg0'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk led[3]~reg0 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[3]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[3]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[4]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[4]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[3]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[3]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[4]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[4]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[3]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[3]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { led[3]~reg0 led[4]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "1.490 ns" { led[3]~reg0 {} led[4]~reg0 {} } { 0.000ns 0.899ns } { 0.000ns 0.591ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[4]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[4]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk led[3]~reg0 } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} led[3]~reg0 {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "clkdiv\[6\] rst clk 8.309 ns register " "Info: tsu for register \"clkdiv\[6\]\" (data pin = \"rst\", clock pin = \"clk\") is 8.309 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.324 ns + Longest pin register " "Info: + Longest pin to register delay is 11.324 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_44 22 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_44; Fanout = 22; PIN Node = 'rst'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.996 ns) + CELL(0.914 ns) 7.042 ns led\[1\]~193 2 COMB LC_X5_Y4_N0 39 " "Info: 2: + IC(4.996 ns) + CELL(0.914 ns) = 7.042 ns; Loc. = LC_X5_Y4_N0; Fanout = 39; COMB Node = 'led\[1\]~193'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.910 ns" { rst led[1]~193 } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.522 ns) + CELL(1.760 ns) 11.324 ns clkdiv\[6\] 3 REG LC_X3_Y3_N9 2 " "Info: 3: + IC(2.522 ns) + CELL(1.760 ns) = 11.324 ns; Loc. = LC_X3_Y3_N9; Fanout = 2; REG Node = 'clkdiv\[6\]'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.282 ns" { led[1]~193 clkdiv[6] } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.806 ns ( 33.61 % ) " "Info: Total cell delay = 3.806 ns ( 33.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.518 ns ( 66.39 % ) " "Info: Total interconnect delay = 7.518 ns ( 66.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.324 ns" { rst led[1]~193 clkdiv[6] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "11.324 ns" { rst {} rst~combout {} led[1]~193 {} clkdiv[6] {} } { 0.000ns 0.000ns 4.996ns 2.522ns } { 0.000ns 1.132ns 0.914ns 1.760ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 45 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns clkdiv\[6\] 2 REG LC_X3_Y3_N9 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y3_N9; Fanout = 2; REG Node = 'clkdiv\[6\]'" {  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk clkdiv[6] } "NODE_NAME" } } { "LED8bit.v" "" { Text "E:/project/EmbeddedProject/MAXII_DEV_BOARD/MAXII_DEV_BOARD_Rev1.0/SoftwareCPLDCode/LED8bit/LED8bit.v" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk clkdiv[6] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} clkdiv[6] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.324 ns" { rst led[1]~193 clkdiv[6] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "11.324 ns" { rst {} rst~combout {} led[1]~193 {} clkdiv[6] {} } { 0.000ns 0.000ns 4.996ns 2.522ns } { 0.000ns 1.132ns 0.914ns 1.760ns } "" } } { "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk clkdiv[6] } "NODE_NAME" } } { "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} clkdiv[6] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}