led8bit.fit.rpt

MAXII_DEV_BOARD EPM240的开发板电路图。

; 17                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+--------------------------------------------------------------------------------------+
; Fitter Device Options                                                                ;
+----------------------------------------------+---------------------------------------+
; Option                                       ; Setting                               ;
+----------------------------------------------+---------------------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                                   ;
; Enable device-wide reset (DEV_CLRn)          ; Off                                   ;
; Enable device-wide output enable (DEV_OE)    ; Off                                   ;
; Enable INIT_DONE output                      ; Off                                   ;
; Configuration scheme                         ; Passive Serial                        ;
; Reserve all unused pins                      ; As input tri-stated with weak pull-up ;
; Base pin-out file on sameframe device        ; Off                                   ;
+----------------------------------------------+---------------------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                        ;
+--------------------------------------------------------------------------------+-------------+
; Name                                                                           ; Value       ;
+--------------------------------------------------------------------------------+-------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff          ;
; Mid Wire Use - Fit Attempt 1                                                   ; 15          ;
; Mid Slack - Fit Attempt 1                                                      ; 76574       ;
; Internal Atom Count - Fit Attempt 1                                            ; 59          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 59          ;
; LAB Count - Fit Attempt 1                                                      ; 8           ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.250       ;
; Inputs per LAB - Fit Attempt 1                                                 ; 7.000       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.875       ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:8         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:4;1:4     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:1;1:4;2:3 ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:1;1:4;2:3 ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:1;1:4;2:3 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:1;1:4;2:3 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:2;1:6     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:8         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:4;1:4     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:7     ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:5;2:2 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:8         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:7     ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:1;1:7     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:8         ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:5;1:3     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:8         ;
; LEs in Chains - Fit Attempt 1                                                  ; 28          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 24          ;
; LABs with Chains - Fit Attempt 1                                               ; 4           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
+--------------------------------------------------------------------------------+-------------+


+--------------------------------------------+
; Advanced Data - Placement                  ;
+------------------------------------+-------+
; Name                               ; Value ;
+------------------------------------+-------+
; Auto Fit Point 2 - Fit Attempt 1   ; ff    ;
; Early Wire Use - Fit Attempt 1     ; 3     ;
; Early Slack - Fit Attempt 1        ; 76313 ;
; Auto Fit Point 4 - Fit Attempt 1   ; ff    ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff    ;
; Mid Wire Use - Fit Attempt 1       ; 7     ;
; Mid Slack - Fit Attempt 1          ; 76313 ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff    ;
; Late Wire Use - Fit Attempt 1      ; 8     ;
; Late Slack - Fit Attempt 1         ; 76313 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000 ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff    ;
; Time - Fit Attempt 1               ; 0     ;
+------------------------------------+-------+


+---------------------------------------------+
; Advanced Data - Routing                     ;
+-------------------------------------+-------+
; Name                                ; Value ;
+-------------------------------------+-------+
; Early Slack - Fit Attempt 1         ; 79133 ;
; Early Wire Use - Fit Attempt 1      ; 7     ;
; Peak Regional Wire - Fit Attempt 1  ; 6     ;
; Mid Slack - Fit Attempt 1           ; 78178 ;
; Late Slack - Fit Attempt 1          ; 78178 ;
; Late Wire Use - Fit Attempt 1       ; 7     ;
; Time - Fit Attempt 1                ; 0     ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.078 ;
+-------------------------------------+-------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Mon Apr 28 22:38:02 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LED8bit -c LED8bit
Info: Selected device EPM240T100C5 for design "LED8bit"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM240T100A5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
    Info: Device EPM570T100A5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 12
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 11.505 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 5; REG Node = 'clkdiv[10]'
    Info: 2: + IC(2.250 ns) + CELL(0.200 ns) = 2.450 ns; Loc. = LAB_X5_Y2; Fanout = 1; COMB Node = 'LessThan1~391'
    Info: 3: + IC(0.440 ns) + CELL(0.740 ns) = 3.