led8bit.v.bak

MAXII_DEV_BOARD EPM240的开发板电路图。

module LED8bit
(
  rst,    //system reset singal    
  clk,    //system clock singal,frequency = 32.768KHz
  led,    //LED driver singal,8bit
  led3,   //three color led
  buzzer,
  led7sel,
  led7data
);
        
input         rst;
input         clk;

output[7:0]   led;
reg[7:0]      led;

output[2:0]   led3;
reg[2:0]      led3;

output        buzzer;
reg           buzzer;

output[5:0]   led7sel;
reg[5:0]      led7sel;

output[7:0]   led7data;
reg[7:0]      led7data;


reg[23:0]     clkdiv;   //system clock divide rate
reg[3:0]      cnt;

always @ (posedge clk)  
if (!rst)
begin
  clkdiv <= 0;
  led <= 8'b0000_0000;
  led3 <= 3'b000;
  buzzer <= 1'b1;
  cnt <= 4'b0000;
  led7sel <= 6'b000000;
  led7data <= 8'b0000_0000;
end  
else
begin
  if (clkdiv < 24'd10000000)
  begin
    clkdiv <= clkdiv + 1'b1;
  end
  else
  begin
    led <= {led[6:0],~led[7]};
    led3 <= led3 + 1'b1; 
    cnt <= cnt + 1'b1;

    case(cnt)
    'b0000:
			begin
				led7data <= 8'hc0;	//0
			end
		'b0001:
			begin
				led7data <= 8'hf9;	//1
			end
		
		'b0010:
			begin
				led7data <= 8'ha4;	//2
			end
		'b0011:
			begin
				led7data <= 8'hb0;	//3
			end
		'b0100:
			begin
				led7data <= 8'h99;	//4
			end
		'b0101:
			begin
				led7data <= 8'h92;	//5
			end
			
		'b0110:
			begin
				led7data <= 8'h82;	//6
			end
			
		'b0111:
			begin
				led7data <= 8'hf8;	//7
			end
			
		'b1000:
			begin
				led7data <= 8'h80;	//8
			end
			
		'b1001:
			begin
				led7data <= 8'h90;	//9
			end
			
		'b1010:
			begin
				led7data <= 8'h88;	//a
			end
			
		'b1011:
			begin
				led7data <= 8'h83;	//b
			end
			
		'b1100:
			begin
				led7data <= 8'hc6;	//c
			end
			
		'b1101:
			begin
				led7data <= 8'ha1;	//d
			end
			
		'b1110:
			begin
				led7data <= 8'h86;	//e
			end
			
		'b1111:
			begin
				led7data <= 8'h8e;	//f
			end
    endcase
    clkdiv <= 0;
  end

  if(clkdiv < 24'd2000000)
  begin
    clkdiv <= clkdiv + 1'b1;
  end
  else
  begin
    buzzer <= ~buzzer;
  end
end 




endmodule