regs_audio.h

i.mx27 soc for wince 6.0

#define MC13783_AUD_RX0_ASPEN_DISABLE            0 //amplifier asp disable
#define MC13783_AUD_RX0_ASPEN_ENABLE            1 //amplifier asp enable

#define MC13783_AUD_RX0_ASPSEL_CODEC            0 //select codec
#define MC13783_AUD_RX0_ASPSEL_RIGHT            1 //select right

#define MC13783_AUD_RX0_ALSPEN_DISABLE            0 //amplifier alsp disable
#define MC13783_AUD_RX0_ALSPEN_ENABLE            1 //amplifier alsp enable

#define MC13783_AUD_RX0_ALSPREF_NOBIAS            0 //bias alsp at common audio reference disable
#define MC13783_AUD_RX0_ALSPREF_BIAS            1 //bias alsp at common audio reference enable

#define MC13783_AUD_RX0_ALSPSEL_CODEC            0 //select codec
#define MC13783_AUD_RX0_ALSPSEL_RIGHT            1 //select right

#define MC13783_AUD_RX0_LSPLEN_DISABLE            0 //output lspl disable
#define MC13783_AUD_RX0_LSPLEN_ENABLE            1 //output lspl enable

#define MC13783_AUD_RX0_AHSREN_DISABLE            0 //amplifier ahsr disable
#define MC13783_AUD_RX0_AHSREN_ENABLE            1 //amplifier ahsr enable

#define MC13783_AUD_RX0_AHSLEN_DISABLE            0 //amplifier ahsl disable
#define MC13783_AUD_RX0_AHSLEN_ENABLE            1 //amplifier ahsl enable

#define MC13783_AUD_RX0_AHSSEL_CODEC            0 //ahsr and ahsl input select codec
#define MC13783_AUD_RX0_AHSSEL_LEFTRIGHT            1 //ahsr and ahsl input select left/right

#define MC13783_AUD_RX0_HSPGDIS_ENABLE            0 //phantom ground enable
#define MC13783_AUD_RX0_HSPGDIS_DISABLE            1 //phantom ground disable

#define MC13783_AUD_RX0_HSDETEN_DISABLE            0 //headset detect disable
#define MC13783_AUD_RX0_HSDETEN_ENABLE            1 //headset detect enable

#define MC13783_AUD_RX0_HSDETAUTO_DISABLE            1 //amplifier not enabled by headset detect
#define MC13783_AUD_RX0_HSDETAUTO_ENABLE            0 //amplifier enabled by headset detect

#define MC13783_AUD_RX0_ARXOUTREN_DISABLE            0 //output rxoutr disable
#define MC13783_AUD_RX0_ARXOUTREN_ENABLE            1 //output rxoutr enable

#define MC13783_AUD_RX0_ARXOUTLEN_DISABLE            0 //output rxoutl disable
#define MC13783_AUD_RX0_ARXOUTLEN_ENABLE            1 //output rxoutl enable

#define MC13783_AUD_RX0_ARXOUTSEL_CODEC            0 //arout input select codec
#define MC13783_AUD_RX0_ARXOUTSEL_LEFTRIGHT            1 //arxout input select left/right

#define MC13783_AUD_RX0_CDCOUTEN_DISABLE            0 //output cdcout disable
#define MC13783_AUD_RX0_CDCOUTEN_ENABLE            1 //output cdcout enable

#define MC13783_AUD_RX0_ADDCDC_NOSELECT            0 //adder channel codec not selected
#define MC13783_AUD_RX0_ADDCDC_SELECT            1 //adder channel codec select

#define MC13783_AUD_RX0_ADDSTDC_NOSELECT            0 //adder channel stereo dac not selected
#define MC13783_AUD_RX0_ADDSTDC_SELECT            1 //adder channel stereo dac select

#define MC13783_AUD_RX0_ADDRXIN_NOSELECT            0 //adder channel line in not selected
#define MC13783_AUD_RX0_ADDRXIN_SELECT            1 //adder channel line in select

// AUD_RX1
#define MC13783_AUD_RX1_PGARXEN_DISABLE            0 //codec receive pga disable
#define MC13783_AUD_RX1_PGARXEN_ENABLE            1 //codec receive pga enable

#define MC13783_AUD_RX1_PGASTEN_DISABLE            0 //stereo dac pga disable
#define MC13783_AUD_RX1_PGASTEN_ENABLE            1 //stereo dac pga enable

#define MC13783_AUD_RX1_ARXINEN_DISABLE            0 //amplifier arx disable
#define MC13783_AUD_RX1_ARXINEN_ENABLE            1 //amplifier arx enable

#define MC13783_AUD_RX1_ARXIN_NOGAIN            0 //amplifier arx no additional gain
#define MC13783_AUD_RX1_ARXIN_ADDGAIN            1 //amplifier arx additional gain

#define MC13783_AUD_RX1_MONO_STEREO           0 // Stereo
#define MC13783_AUD_RX1_MONO_STEREO_OPP       1 // Stereo opposite phase
#define MC13783_AUD_RX1_MONO_STEREO2MONO      2 // Stereo to mono conversion
#define MC13783_AUD_RX1_MONO_MONO_OPP         3 // Mono opposite

#define MC13783_AUD_RX1_BALLR_RIGHT            0 //right channel balance
#define MC13783_AUD_RX1_BALLR_LEFT            1 //left channel balance

//AUD_TX
#define MC13783_AUD_TX_MC1BEN_DISABLE            0 //microphone bias 1 disable
#define MC13783_AUD_TX_MC1BEN_ENABLE            1 //microphone bias 1 enable

#define MC13783_AUD_TX_MC2BEN_DISABLE           0 //microphone bias 2 disable
#define MC13783_AUD_TX_MC2BEN_ENABLE           1 //microphone bias 2 enable

#define MC13783_AUD_TX_MC2BDETEN_DISABLE            0 //microphone bias 2 detect disable
#define MC13783_AUD_TX_MC2BDETEN_ENABLE            1 //microphone bias 2 detect enable

#define MC13783_AUD_TX_AMC1REN_DISABLE            0 //amplifier amc1r disable
#define MC13783_AUD_TX_AMC1REN_ENABLE            1 //amplifier amc1r enable

#define MC13783_AUD_TX_AMC1LEN_DISABLE            0 //amplifier amc1l disable
#define MC13783_AUD_TX_AMC1LEN_ENABLE            1 //amplifier amc1l enable

#define MC13783_AUD_TX_AMC2EN_DISABLE           0 //amplifier amc2 disable
#define MC13783_AUD_TX_AMC2EN_ENABLE           1 //amplifier amc2 enable

#define MC13783_AUD_TX_AMC_MODE_VTOV            0 //amplifier voltage to voltage mode
#define MC13783_AUD_TX_AMC_MODE_ITOV            1 //amplifier current to voltage mode

#define MC13783_AUD_TX_ATXINEN_DISABLE            0 //amplifier atxin disable
#define MC13783_AUD_TX_ATXINEN_ENABLE            1 //amplifier atxin enable

#define MC13783_AUD_TX_ATXOUTEN_DISABLE            0 //output txout disable
#define MC13783_AUD_TX_ATXOUTEN_ENABLE            1 //output txout enable

//SSI_NW
#define MC13783_SSI_NW_SUMGAIN_0DB            0 //Summed receive signal gain setting 0dB
#define MC13783_SSI_NW_SUMGAIN_MINUS6DB            1 //summed receive signal gain setting -6dB

#define MC13783_SSI_NW_RXSECGAIN_NOMIX            0 //no mixing
#define MC13783_SSI_NW_RXSECGAIN_0DB            1 //0dB
#define MC13783_SSI_NW_RXSECGAIN_MINUS6DB            2 //-6dB
#define MC13783_SSI_NW_RXSECGAIN_MINUS12DB            3 //-12dB

//AUD_CDC
#define MC13783_AUD_CDC_CDCSSISEL_PATH1            0 //codec ssi bus select rx1, bcl1, fs1
#define MC13783_AUD_CDC_CDCSSISEL_PATH2            1 //codec ssi bus select rx2, bcl2, fs2

#define MC13783_AUD_CDC_CDCCLKSEL_CLIA            0 //codec clock input select CLIA
#define MC13783_AUD_CDC_CDCCLKSEL_CLIB            1 //codec clock input select CLIB

#define MC13783_AUD_CDC_CDCSM_MASTER            0 //codec master select
#define MC13783_AUD_CDC_CDCSM_SLAVE            1 //codec slave select

#define MC13783_AUD_CDC_CDCBCLINV_NOINVERT            0 //codec bitclock inversion disable
#define MC13783_AUD_CDC_CDCBCLINV_INVERT            1 //codec bitclock inversion enable

#define MC13783_AUD_CDC_CDCFSINV_NOINVERT            0 //codec framesync inversion disable
#define MC13783_AUD_CDC_CDCFSINV_INVERT            1 //codec framesync inversion enable

#define MC13783_AUD_CDC_CDCFSOFFSET_MINUS1            0 //codec framesync offset select -1
#define MC13783_AUD_CDC_CDCFSOFFSET_ZERO            1 //codec framesync offset select 0

#define MC13783_AUD_CDC_CDCFSLONG_SHORT            0 //codec long framesync select short
#define MC13783_AUD_CDC_CDCFSLONG_LONG            1 //codec long framesync select long

#define MC13783_AUD_CDC_CDCFS8K16K_8K            0 //codec framesync select 8k
#define MC13783_AUD_CDC_CDCFS8K16K_16K            1 //codec framesync select 16k

#define MC13783_AUD_CDC_CDCEN_DISABLE            0 //codec disable
#define MC13783_AUD_CDC_CDCEN_ENABLE            1 //codec enable

#define MC13783_AUD_CDC_CDCCLKEN_DISABLE            0 //codec clocking disable
#define MC13783_AUD_CDC_CDCCLKEN_ENABLE            1 //codec clocking enable

#define MC13783_AUD_CDC_CDCTS_NONTRISTATE            0 //codec ssi non tristate
#define MC13783_AUD_CDC_CDCTS_TRISTATE            1 //codec ssi FS, TX and BCL are tristate

#define MC13783_AUD_CDC_CDCDITH_ENABLE            0 //codec dithering enable
#define MC13783_AUD_CDC_CDCDITH_DISABLE            1 //codec dithering disable

#define MC13783_AUD_CDC_CDCRESET_NORESET            0 //codec filter no reset
#define MC13783_AUD_CDC_CDCRESET_RESET            1 //codec filter reset

#define MC13783_AUD_CDC_CDCBYP_NOBYPASS            0 //codec no bypass
#define MC13783_AUD_CDC_CDCBYP_BYPASS            1 //codec bypass

#define MC13783_AUD_CDC_CDCALM_DISABLE            0 //codec analog loopback disable
#define MC13783_AUD_CDC_CDCALM_ENABLE            1 //codec analog loopback enable

#define MC13783_AUD_CDC_CDCDLM_DISABLE            0 //codec digital loopback disable
#define MC13783_AUD_CDC_CDCDLM_ENABLE            1 //codec digital loopback enable

#define MC13783_AUD_CDC_AUDIHPF_DISABLE            0 //transmit high pass filter disable
#define MC13783_AUD_CDC_AUDIHPF_ENABLE            1 //transmit high pass filter enable

#define MC13783_AUD_CDC_AUDOHPF_DISABLE            0 //receive high pass filter disable
#define MC13783_AUD_CDC_AUDOHPF_ENABLE            1 //receive high pass filter enable


//AUD_STR_DAC
#define MC13783_AUD_STR_DAC_STDCSSISEL_PATH1            0 //stereo dac ssi bus select rx1, fs1, bcl1
#define MC13783_AUD_STR_DAC_STDCSSISEL_PATH2            1 //stereo dac ssi bus select rx2, fs2, bcl2

#define MC13783_AUD_STR_DAC_STDCCLKSEL_CLIA            0 //stereo dac clock input select CLIA
#define MC13783_AUD_STR_DAC_STDCCLKSEL_CLIB            1 //stereo dac clock input select CLIB

#define MC13783_AUD_STR_DAC_STDCSM_MASTER            0 //stereo dac master mode select
#define MC13783_AUD_STR_DAC_STDCSM_SLAVE            1 //stereo dac slave mode select

#define MC13783_AUD_STR_DAC_STDCBCLINV_NOINVERT            0 //stereo dac bitclock inversion disable
#define MC13783_AUD_STR_DAC_STDCBCLINV_INVERT            1 //stereo dac bitclock inversion enable

#define MC13783_AUD_STR_DAC_STDCFSINV_NOINVERT            0 //stereo dac framesync inversion disable
#define MC13783_AUD_STR_DAC_STDCFSINV_INVERT            1 //stereo dac framesync inversion enable

#define MC13783_AUD_STR_DAC_STDCFS_NORMAL                 0 // Normal mode timing
#define MC13783_AUD_STR_DAC_STDCFS_NETWORK                1 // Network mode timing
#define MC13783_AUD_STR_DAC_STDCFS_I2S                    2 // I2S mode timing

#define MC13783_AUD_STR_DAC_STDCCLK_13MHZ                 0 // CLI = 13 MHz (master)
#define MC13783_AUD_STR_DAC_STDCCLK_15_36MHZ              1 // CLI = 15.36 MHz (master)
#define MC13783_AUD_STR_DAC_STDCCLK_16_8MHZ               2 // CLI = 16.8 MHz (master)
#define MC13783_AUD_STR_DAC_STDCCLK_26MHZ                 4 // CLI = 26 MHz (master)
#define MC13783_AUD_STR_DAC_STDCCLK_12MHZ                 5 // CLI = 12 MHz (master)
#define MC13783_AUD_STR_DAC_STDCCLK_3_6864MHZ             6 // CLI = 3.6864 MHz (master)
#define MC13783_AUD_STR_DAC_STDCCLK_33_6MHZ               7 // CLI = 33.6 MHz (master)
#define MC13783_AUD_STR_DAC_STDCCLK_MCL                   5 // CLI = MCL, PLL off (slave)
#define MC13783_AUD_STR_DAC_STDCCLK_FS                    6 // FS (slave)
#define MC13783_AUD_STR_DAC_STDCCLK_BCL                   7 // BCL (slave)

#define MC13783_AUD_STR_DAC_STDCEN_DISABLE            0 //stereo dac disable
#define MC13783_AUD_STR_DAC_STDCEN_ENABLE            1 //stereo dac enable

#define MC13783_AUD_STR_DAC_STDCCLKEN_DISABLE            0 //stereo dac clocking disable
#define MC13783_AUD_STR_DAC_STDCCLKEN_ENABLE            1 //stereo dac clocking enable

#define MC13783_AUD_STR_DAC_STDCRESET_NORESET            0 //stereo dac filter no reset
#define MC13783_AUD_STR_DAC_STDCRESET_RESET            1 //stereo dac filter reset

#define MC13783_AUD_STR_DAC_SPDIF_DISABLE            0 //stereo dac ssi spdif mode disable
#define MC13783_AUD_STR_DAC_SPDIF_ENABLE            1 //stereo dac ssi spdif mode enable

#define MC13783_AUD_STR_DAC_SR_8000                       0 // FS = 8 KHz
#define MC13783_AUD_STR_DAC_SR_11025                      1 // FS = 11.025 KHz
#define MC13783_AUD_STR_DAC_SR_12000                      2 // FS = 12 KHz
#define MC13783_AUD_STR_DAC_SR_16000                      3 // FS = 16 KHz
#define MC13783_AUD_STR_DAC_SR_22050                      4 // FS = 22.050 KHz
#define MC13783_AUD_STR_DAC_SR_24000                      5 // FS = 24 KHz
#define MC13783_AUD_STR_DAC_SR_32000                      6 // FS = 32 KHz
#define MC13783_AUD_STR_DAC_SR_44100                      7 // FS = 44.1 KHz
#define MC13783_AUD_STR_DAC_SR_48000                      8 // FS = 48 KHz
#define MC13783_AUD_STR_DAC_SR_64000                      9 // FS = 64 KHz
#define MC13783_AUD_STR_DAC_SR_96000                      10 // FS = 96 KHz

#ifdef __cplusplus
}
#endif

#endif // __MC13783_REGS_AUDIO_H__