regs_audio.h

i.mx27 soc for wince 6.0

//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004-2005, Motorola Inc. All Rights Reserved
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
//  Header:  regs_audio.h
//
//  This header file defines audio registers of MC13783.
//
//------------------------------------------------------------------------------

#ifndef __MC13783_REGS_AUDIO_H__
#define __MC13783_REGS_AUDIO_H__

#ifdef __cplusplus
extern "C" {
#endif

//------------------------------------------------------------------------------
// GENERAL MODULE CONSTANTS
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// REGISTER BIT FIELD POSITIONS (LEFT SHIFT)
//------------------------------------------------------------------------------
#define MC13783_AUD_RX0_VAUDIOON_LSH            0
#define MC13783_AUD_RX0_BIASEN_LSH            1
#define MC13783_AUD_RX0_BIASSPEED_LSH            2
#define MC13783_AUD_RX0_ASPEN_LSH            3
#define MC13783_AUD_RX0_ASPSEL_LSH            4
#define MC13783_AUD_RX0_ALSPEN_LSH            5
#define MC13783_AUD_RX0_ALSPREF_LSH            6
#define MC13783_AUD_RX0_ALSPSEL_LSH            7
#define MC13783_AUD_RX0_LSPLEN_LSH            8
#define MC13783_AUD_RX0_AHSREN_LSH            9
#define MC13783_AUD_RX0_AHSLEN_LSH            10
#define MC13783_AUD_RX0_AHSSEL_LSH            11
#define MC13783_AUD_RX0_HSPGDIS_LSH            12
#define MC13783_AUD_RX0_HSDETEN_LSH            13
#define MC13783_AUD_RX0_HSDETAUTO_LSH            14
#define MC13783_AUD_RX0_ARXOUTREN_LSH            15
#define MC13783_AUD_RX0_ARXOUTLEN_LSH            16
#define MC13783_AUD_RX0_ARXOUTSEL_LSH            17
#define MC13783_AUD_RX0_CDCOUTEN_LSH            18
#define MC13783_AUD_RX0_ADDCDC_LSH            21
#define MC13783_AUD_RX0_ADDSTDC_LSH            22
#define MC13783_AUD_RX0_ADDRXIN_LSH            23

#define MC13783_AUD_RX1_PGARXEN_LSH            0
#define MC13783_AUD_RX1_PGARX_LSH            1
#define MC13783_AUD_RX1_PGASTEN_LSH            5
#define MC13783_AUD_RX1_PGAST_LSH            6
#define MC13783_AUD_RX1_ARXINEN_LSH            10
#define MC13783_AUD_RX1_ARXIN_LSH            11
#define MC13783_AUD_RX1_PGARXIN_LSH            12
#define MC13783_AUD_RX1_MONO_LSH            16
#define MC13783_AUD_RX1_BAL_LSH            18
#define MC13783_AUD_RX1_BALLR_LSH            21

#define MC13783_AUD_TX_MC1BEN_LSH            0
#define MC13783_AUD_TX_MC2BEN_LSH            1
#define MC13783_AUD_TX_MC2BDETEN_LSH            3
#define MC13783_AUD_TX_AMC1REN_LSH            5
#define MC13783_AUD_TX_AMC1RITOV_LSH            6
#define MC13783_AUD_TX_AMC1LEN_LSH            7
#define MC13783_AUD_TX_AMC1LITOV_LSH            8
#define MC13783_AUD_TX_AMC2EN_LSH            9
#define MC13783_AUD_TX_AMC2ITOV_LSH            10
#define MC13783_AUD_TX_ATXINEN_LSH            11
#define MC13783_AUD_TX_ATXOUTEN_LSH            12
#define MC13783_AUD_TX_PGATXR_LSH            14
#define MC13783_AUD_TX_PGATXL_LSH            19

#define MC13783_SSI_NW_CDCTXRXSLOT_LSH            2
#define MC13783_SSI_NW_CDCTXSECSLOT_LSH            4
#define MC13783_SSI_NW_CDCRXSECSLOT_LSH            6
#define MC13783_SSI_NW_CDCRXSECGAIN_LSH            8
#define MC13783_SSI_NW_CDCSUMGAIN_LSH            10
#define MC13783_SSI_NW_STDCSLOT_LSH            12
#define MC13783_SSI_NW_STDCRXSLOT_LSH            14
#define MC13783_SSI_NW_STDCRXSECSLOT_LSH            16
#define MC13783_SSI_NW_STDCRXSECGAIN_LSH            18
#define MC13783_SSI_NW_STDCSUMGAIN_LSH            20

#define MC13783_AUD_CDC_CDCSSISEL_LSH            0
#define MC13783_AUD_CDC_CDCCLKSEL_LSH            1
#define MC13783_AUD_CDC_CDCSM_LSH            2
#define MC13783_AUD_CDC_CDCBCLINV_LSH            3
#define MC13783_AUD_CDC_CDCFSINV_LSH            4
#define MC13783_AUD_CDC_CDCFSOFFSET_LSH            5
#define MC13783_AUD_CDC_CDCFSLONG_LSH            6
#define MC13783_AUD_CDC_CDCCLK_LSH            7
#define MC13783_AUD_CDC_CDCFS8K16K_LSH            10
#define MC13783_AUD_CDC_CDCEN_LSH            11
#define MC13783_AUD_CDC_CDCCLKEN_LSH            12
#define MC13783_AUD_CDC_CDCTS_LSH            13
#define MC13783_AUD_CDC_CDCDITH_LSH            14
#define MC13783_AUD_CDC_CDCRESET_LSH            15
#define MC13783_AUD_CDC_CDCBYP_LSH            16
#define MC13783_AUD_CDC_CDCALM_LSH            17
#define MC13783_AUD_CDC_CDCDLM_LSH            18
#define MC13783_AUD_CDC_AUDIHPF_LSH            19
#define MC13783_AUD_CDC_AUDOHPF_LSH            20

#define MC13783_AUD_STR_DAC_STDCSSISEL_LSH            0
#define MC13783_AUD_STR_DAC_STDCCLKSEL_LSH            1
#define MC13783_AUD_STR_DAC_STDCSM_LSH            2
#define MC13783_AUD_STR_DAC_STDCBCLINV_LSH            3
#define MC13783_AUD_STR_DAC_STDCFSINV_LSH            4
#define MC13783_AUD_STR_DAC_STDCFS_LSH            5
#define MC13783_AUD_STR_DAC_STDCCLK_LSH            7
#define MC13783_AUD_STR_DAC_STDCEN_LSH            11
#define MC13783_AUD_STR_DAC_STDCCLKEN_LSH            12
#define MC13783_AUD_STR_DAC_STDCRESET_LSH            15
#define MC13783_AUD_STR_DAC_SPDIF_LSH            16
#define MC13783_AUD_STR_DAC_SR_LSH            17


//------------------------------------------------------------------------------
// REGISTER BIT FIELD WIDTHS
//------------------------------------------------------------------------------
#define MC13783_AUD_RX0_VAUDIOON_WID            1
#define MC13783_AUD_RX0_BIASEN_WID            1
#define MC13783_AUD_RX0_BIASSPEED_WID            1
#define MC13783_AUD_RX0_ASPEN_WID            1
#define MC13783_AUD_RX0_ASPSEL_WID            1
#define MC13783_AUD_RX0_ALSPEN_WID            1
#define MC13783_AUD_RX0_ALSPREF_WID            1
#define MC13783_AUD_RX0_ALSPSEL_WID            1
#define MC13783_AUD_RX0_LSPLEN_WID            1
#define MC13783_AUD_RX0_AHSREN_WID            1
#define MC13783_AUD_RX0_AHSLEN_WID            1
#define MC13783_AUD_RX0_AHSSEL_WID            1
#define MC13783_AUD_RX0_HSPGDIS_WID            1
#define MC13783_AUD_RX0_HSDETEN_WID            1
#define MC13783_AUD_RX0_HSDETAUTO_WID            1
#define MC13783_AUD_RX0_ARXOUTREN_WID            1
#define MC13783_AUD_RX0_ARXOUTLEN_WID            1
#define MC13783_AUD_RX0_ARXOUTSEL_WID            1
#define MC13783_AUD_RX0_CDCOUTEN_WID            1
#define MC13783_AUD_RX0_ADDCDC_WID            1
#define MC13783_AUD_RX0_ADDSTDC_WID            1
#define MC13783_AUD_RX0_ADDRXIN_WID            1

#define MC13783_AUD_RX1_PGARXEN_WID            1
#define MC13783_AUD_RX1_PGARX_WID            4
#define MC13783_AUD_RX1_PGASTEN_WID            1
#define MC13783_AUD_RX1_PGAST_WID            4
#define MC13783_AUD_RX1_ARXINEN_WID            1
#define MC13783_AUD_RX1_ARXIN_WID            1
#define MC13783_AUD_RX1_PGARXIN_WID            4
#define MC13783_AUD_RX1_MONO_WID            2
#define MC13783_AUD_RX1_BAL_WID            3
#define MC13783_AUD_RX1_BALLR_WID            1

#define MC13783_AUD_TX_MC1BEN_WID            1
#define MC13783_AUD_TX_MC2BEN_WID            1
#define MC13783_AUD_TX_MC2BDETEN_WID            1
#define MC13783_AUD_TX_AMC1REN_WID            1
#define MC13783_AUD_TX_AMC1RITOV_WID            1
#define MC13783_AUD_TX_AMC1LEN_WID            1
#define MC13783_AUD_TX_AMC1LITOV_WID            1
#define MC13783_AUD_TX_AMC2EN_WID           1
#define MC13783_AUD_TX_AMC2ITOV_WID            1
#define MC13783_AUD_TX_ATXINEN_WID            1
#define MC13783_AUD_TX_ATXOUTEN_WID            1
#define MC13783_AUD_TX_PGATXR_WID            5
#define MC13783_AUD_TX_PGATXL_WID            5

#define MC13783_SSI_NW_CDCTXRXSLOT_WID            2
#define MC13783_SSI_NW_CDCTXSECSLOT_WID            2
#define MC13783_SSI_NW_CDCRXSECSLOT_WID            2
#define MC13783_SSI_NW_CDCRXSECGAIN_WID            2
#define MC13783_SSI_NW_CDCSUMGAIN_WID            1
#define MC13783_SSI_NW_STDCSLOT_WID            2
#define MC13783_SSI_NW_STDCRXSLOT_WID            2
#define MC13783_SSI_NW_STDCRXSECSLOT_WID            2
#define MC13783_SSI_NW_STDCRXSECGAIN_WID            2
#define MC13783_SSI_NW_STDCSUMGAIN_WID            1

#define MC13783_AUD_CDC_CDCSSISEL_WID            1
#define MC13783_AUD_CDC_CDCCLKSEL_WID            1
#define MC13783_AUD_CDC_CDCSM_WID            1
#define MC13783_AUD_CDC_CDCBCLINV_WID            1
#define MC13783_AUD_CDC_CDCFSINV_WID            1
#define MC13783_AUD_CDC_CDCFSOFFSET_WID            1
#define MC13783_AUD_CDC_CDCFSLONG_WID            1
#define MC13783_AUD_CDC_CDCCLK_WID            3
#define MC13783_AUD_CDC_CDCFS8K16K_WID            1
#define MC13783_AUD_CDC_CDCEN_WID            1
#define MC13783_AUD_CDC_CDCCLKEN_WID            1
#define MC13783_AUD_CDC_CDCTS_WID            1
#define MC13783_AUD_CDC_CDCDITH_WID            1
#define MC13783_AUD_CDC_CDCRESET_WID            1
#define MC13783_AUD_CDC_CDCBYP_WID            1
#define MC13783_AUD_CDC_CDCALM_WID            1
#define MC13783_AUD_CDC_CDCDLM_WID            1
#define MC13783_AUD_CDC_AUDIHPF_WID            1
#define MC13783_AUD_CDC_AUDOHPF_WID            1

#define MC13783_AUD_STR_DAC_STDCSSISEL_WID            1
#define MC13783_AUD_STR_DAC_STDCCLKSEL_WID            1
#define MC13783_AUD_STR_DAC_STDCSM_WID            1
#define MC13783_AUD_STR_DAC_STDCBCLINV_WID            1
#define MC13783_AUD_STR_DAC_STDCFSINV_WID            1
#define MC13783_AUD_STR_DAC_STDCFS_WID            2
#define MC13783_AUD_STR_DAC_STDCCLK_WID            3
#define MC13783_AUD_STR_DAC_STDCEN_WID            1
#define MC13783_AUD_STR_DAC_STDCCLKEN_WID            1
#define MC13783_AUD_STR_DAC_STDCRESET_WID            1
#define MC13783_AUD_STR_DAC_SPDIF_WID            1
#define MC13783_AUD_STR_DAC_SR_WID            4


//------------------------------------------------------------------------------
// REGISTER BIT WRITE VALUES
//------------------------------------------------------------------------------

// AUD_RX0
#define MC13783_AUD_RX0_VAUDIOON_DISABLE            0 //no effect
#define MC13783_AUD_RX0_VAUDIOON_FORCE            1 //force vaudio in active on mode

#define MC13783_AUD_RX0_BIASEN_DISABLE            0 //audio bias disable
#define MC13783_AUD_RX0_BIASEN_ENABLE            1 //audio bias enable

#define MC13783_AUD_RX0_BIASSPEED_DISABLE            0 //ramp speed disable
#define MC13783_AUD_RX0_BIASSPEED_ENABLE            1 //ramp speed enable