📄 t1_tx_moto.asl
字号:
00B8 06 00 C2 186 brz ir_transmit_low_00
00BB F0 31 187 lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
00BD CB FE 188 anda #c_prtc0_0
00BF FC 31 189 sta r_prtc
00C1 24 190 ret
00C2 191 ir_transmit_low_00:
00C2 F3 01 192 lda #1
00C4 FD 0B 193 sta flg_ir_transmit_high ;1 stop 38k
00C6 F3 00 194 lda #0
00C8 FD 06 195 sta cnt_ir_transmit ;repeat start counting
00CA F0 31 196 lda r_prtc ;when prtc.0 is high, not transmit ir.
00CC DB 01 197 ora #c_prtc0_1 ;把PC[1]置高
00CE FC 31 198 sta r_prtc
00D0 24 199 ret
00D1 200 ir_tx_data_low_over:
00D1 F1 06 201 lda cnt_ir_transmit
00D3 A7 04 202 cmpe #cnt_ir_tx_stop
00D5 06 00 DF 203 brz ir_tx_end
00D8 F0 31 204 lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
00DA CB FE 205 anda #c_prtc0_0 ;wait for end
00DC FC 31 206 sta r_prtc
00DE 24 207 ret
00DF 208 ir_tx_end:
00DF F3 00 209 lda #0
00E1 FD 0A 210 sta status_ir_transmit
00E3 FD 06 211 sta cnt_ir_transmit
00E5 FD 0B 212 sta flg_ir_transmit_high ;1 stop 38k
00E7 F0 31 213 lda r_prtc ;when prtc.0 is high, not transmit ir.
00E9 DB 01 214 ora #c_prtc0_1 ;把PC[1]置高
00EB FC 31 215 sta r_prtc
00ED 24 216 ret
+ 217
+ 218 ;--------------------Play PCM----------------------------------------------
00EE 219 Pcm_Play:
00EE F1 10 220 lda M_sphptr+2
00F0 FC 54 221 sta r_tpp
00F2 F1 0F 222 lda M_sphptr+1
00F4 FC 02 223 sta r_tph
00F6 F1 0E 224 lda M_sphptr
00F8 FC 01 225 sta r_tpl
00FA 1F 226 inca
00FB FD 0E 227 sta M_sphptr
00FD F3 00 228 lda #00h
00FF 99 0F 229 addc M_sphptr+1
0101 FD 0F 230 sta M_sphptr+1
0103 F3 00 231 lda #00h
0105 99 10 232 addc M_sphptr+2
0107 FD 10 233 sta M_sphptr+2
+ 234 ;//20040630,since the rom size is smaller than 64k, as for 89c21,the following code is redundancy
+ 235 ;loop_rom_ready:
+ 236 ; lda r_op1 ;if data rom grand than 64k
+ 237 ; anda #10000000b ;program must detect OP1[7]
+ 238 ; brz loop_rom_ready ;or add 5us delay in program
0109 F8 239 ldv
010A EB FF 240 xora #0xFF
010C 06 01 14 241 brz 10$
010F EB FF 242 xora #0xFF
0111 FD 12 243 sta M_pcmdata
0113 24 244 ret
+ 245 10$:
0114 F3 FF 246 lda #0xFF
0116 FD 11 247 sta M_stopbit
0118 248 play_over:
+ 249 ;call tail
+ 250 ; lda #00h
+ 251 ; sta r_voc ;close PWM and D/A
0118 24 252 ret
+ 253 ;----------------------------------------------------------------;
+ 254 ;Motor Control Pulse Subroutine
+ 255 ;Motor 1 driver circuit controlled by the input1,input2.
+ 256 ;Motor 2 driver circuit controlled by the input3,input4.
+ 257 ;Motor1: input1-----PRTD.3 Motor2: input3-----PRTD.5
+ 258 ; input2-----PRTD.4 input4-----PRTD.6
+ 259 ;----------------------------------------------------------------;
0119 260 motor_control_pulse::
0119 F1 03 261 lda cnt_timer1
011B 1F 262 inca
011C FD 03 263 sta cnt_timer1
011E A5 00 264 cmpe m_ctrl_t1 ;这寄存器在查表中得到
0120 06 01 29 265 brz ctrl_pulse_1st_part
0123 A5 00 266 cmpe m_ctrl_t2
0125 06 01 32 267 brz ctrl_pulse_2nd_part
0128 24 268 ret
0129 269 ctrl_pulse_1st_part: ;
0129 F0 32 270 lda r_prtd
012B D9 00 271 ora m_prtd_ctrl_1_1 ;不理解为什么这样做(是输出高电平吗？但好象****）
012D FC 32 272 sta r_prtd ;PWM valid levels are finished,will output high to all(the 2cnd level)
012F 02 01 5F 273 br motor_ctrl_pulse_end
0132 274 ctrl_pulse_2nd_part:
0132 F0 32 275 lda r_prtd
0134 C9 00 276 anda m_prtd_ctrl_2_0
0136 D9 00 277 ora m_prtd_ctrl_2_1
0138 FC 32 278 sta r_prtd
013A F3 00 279 lda #00h
013C FD 03 280 sta cnt_timer1
+ 281 ;adda #00h ;clear c
013E F1 04 282 lda cnt_ctrl_pulse ;时间长度计数
0140 1F 283 inca
0141 FD 04 284 sta cnt_ctrl_pulse
0143 F1 05 285 lda cnt_ctrl_pulse+1
0145 9B 00 286 addc #00h
0147 FD 05 287 sta cnt_ctrl_pulse+1
0149 A5 01 288 cmpe m_ctrl_pulse+1 ;counter's high 8bit compare with the set value
014B 07 01 5F 289 brnz motor_ctrl_pulse_end ;if it is lower than the set value, go on counting.
014E F1 04 290 lda cnt_ctrl_pulse
0150 A5 00 291 cmpe m_ctrl_pulse ;counter's low 8bit compare with the set vlaue
0152 07 01 5F 292 brnz motor_ctrl_pulse_end ;if it is lower than the set value, go on counting.
0155 F3 00 293 lda #00h ;/*04-02-19*/
0157 FD 04 294 sta cnt_ctrl_pulse
0159 FD 05 295 sta cnt_ctrl_pulse+1
015B F3 01 296 lda #1
015D FD 00 297 sta flg_new_random
015F 298 motor_ctrl_pulse_end:
015F 24 299 ret
+ 300
+
+Symbol Table
+
+ 1 M_pcmdata 0012 GR
+ 1 M_sphptr 000E GR
+ 1 M_stopbit 0011 GR
+ 2 Pcm_Play 00EE R
+ c_ir_group = 000C
+ c_ir_transmit = 0005
+ c_ir_transmit_h = 000D
+ c_ir_transmit_l = 0005
+ c_ir_tx_data = 000F
+ c_prtc0_0 = 00FE
+ c_prtc0_1 = 0001
+ c_prtd012_1 = 0007
+ c_prtd0_1 = 0001
+ c_prtd1_1 = 0002
+ c_prtd2_1 = 0004
+ 1 cnt_ctrl_pulse 0004 GR
+ 1 cnt_ir_rcv 0007 GR
+ cnt_ir_rcv_max = 001D
+ 1 cnt_ir_transmit 0006 GR
+ cnt_ir_transmit_high = 0004
+ 1 cnt_ir_tx_data 000C GR
+ cnt_ir_tx_data_0 = 0004
+ cnt_ir_tx_data_1 = 000C
+ cnt_ir_tx_lead = 0014
+ cnt_ir_tx_stop = 0004
+ 1 cnt_timer1 0003 GR
+ 2 ctrl_pulse_1st_part 0129 R
+ 2 ctrl_pulse_2nd_part 0132 R
+ 1 flg_ir_judge 0008 GR
+ 1 flg_ir_transmit 0009 GR
+ 1 flg_ir_transmit_high 000B GR
+ 1 flg_ir_tx_1 000D GR
+ flg_new_random **** GX
+ 2 ir_transmit 0040 R
+ 2 ir_transmit_data_1 00B4 R
+ 2 ir_transmit_data_low 009A R
+ 2 ir_transmit_low 0081 R
+ 2 ir_transmit_low_00 00C2 R
+ 2 ir_transmit_next_bit 0054 R
+ 2 ir_transmit_over 007A R
+ 2 ir_tx_data_low_over 00D1 R
+ 2 ir_tx_end 00DF R
+ m_ctrl_pulse **** GX
+ m_ctrl_t1 **** GX
+ m_ctrl_t2 **** GX
+ m_prtd_ctrl_1_1 **** GX
+ m_prtd_ctrl_2_0 **** GX
+ m_prtd_ctrl_2_1 **** GX
+ 2 motor_control_pulse 0119 GR
+ 2 motor_ctrl_pulse_end 015F R
+ 2 p_skip_tx 0017 R
+ 2 play_over 0118 R
+ status_ir_rcv **** GX
+ 1 status_ir_transmit 000A GR
+ 2 t1_isr 0000 GR
+ 2 t1_isr_end 0035 R
+ 2 t1_isr_play 0027 R
+ 1 temp_a_1 0000 GR
+ 1 temp_dp_1 0002 GR
+ 1 temp_op1_1 0001 GR
+
+
+Area Table
+
+ 0 . size 0 flags 0
+ 1 time1_var size 13 flags 2
+ 2 timer1_isr size 160 flags 1
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