📄 mouse_timer1.asl
字号:
00CE FC 31 236 sta r_prtc
00D0 24 237 ret
+ 238
+ 239
+ 240
+ 241
00D1 242 ir_tx_data_low_over:
00D1 F1 06 243 lda cnt_ir_transmit
00D3 A7 04 244 cmpe #cnt_ir_tx_stop
00D5 06 00 DF 245 brz ir_tx_end
00D8 F0 31 246 lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
00DA CB FE 247 anda #c_prtc0_0 ;wait for end
00DC FC 31 248 sta r_prtc
00DE 24 249 ret
00DF 250 ir_tx_end:
00DF F3 00 251 lda #0
00E1 FD 0A 252 sta status_ir_transmit
00E3 FD 06 253 sta cnt_ir_transmit
00E5 FD 0B 254 sta flg_ir_transmit_high ;1 stop 38k
00E7 F0 31 255 lda r_prtc ;when prtc.0 is high, not transmit ir.
00E9 DB 01 256 ora #c_prtc0_1 ;把PC[1]置高
00EB FC 31 257 sta r_prtc
00ED 24 258 ret
+ 259
+ 260 ;ir_transmit_low_1:
+ 261 ; cmpe #2 ;is data1?
+ 262 ; brnz ir_transmit_low_2
+ 263 ; lda cnt_ir_transmit
+ 264 ; cmpe #cnt_ir_tx_data1
+ 265 ; brz ir_transmit_low_00
+ 266 ; lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
+ 267 ; anda #c_prtc0_0
+ 268 ; sta r_prtc
+ 269 ; ret
+ 270 ;ir_transmit_low_2:
+ 271 ; cmpe #3 ;is data2?
+ 272 ; brnz ir_transmit_low_3
+ 273 ; lda cnt_ir_transmit
+ 274 ; cmpe #cnt_ir_tx_data2
+ 275 ; brz ir_transmit_low_00
+ 276 ; lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
+ 277 ; anda #c_prtc0_0
+ 278 ; sta r_prtc
+ 279 ; ret
+ 280 ;ir_transmit_low_3:
+ 281 ; cmpe #4 ;is data1 reverse?
+ 282 ; brnz ir_transmit_low_4
+ 283 ; lda cnt_ir_transmit
+ 284 ; cmpe #cnt_ir_tx_data1r
+ 285 ; brz ir_transmit_low_00
+ 286 ; lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
+ 287 ; anda #c_prtc0_0
+ 288 ; sta r_prtc
+ 289 ; ret
+ 290 ;ir_transmit_low_4:
+ 291 ; cmpe #5 ;is data2 reverse?
+ 292 ; brnz ir_transmit_low_5
+ 293 ; lda cnt_ir_transmit
+ 294 ; cmpe #cnt_ir_tx_data2r
+ 295 ; brz ir_transmit_low_00
+ 296 ; lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
+ 297 ; anda #c_prtc0_0
+ 298 ; sta r_prtc
+ 299 ; ret
+ 300 ;ir_transmit_low_5:
+ 301 ;; cmpe #6 ;is stop bit?
+ 302 ;; brnz ir_transmit_low_6
+ 303 ; lda cnt_ir_transmit
+ 304 ; cmpe #cnt_ir_tx_stop
+ 305 ; brz ir_transmit_low6
+ 306 ; lda r_prtc ;continue tx 38k,when prtc.0 is low, 38k carrier pulse pass-by.
+ 307 ; anda #c_prtc0_0
+ 308 ; sta r_prtc
+ 309 ; ret
+ 310 ;ir_transmit_low6:
+ 311 ; lda #0
+ 312 ; sta status_ir_transmit
+ 313 ; sta cnt_ir_transmit
+ 314 ; sta flg_ir_transmit_high ;1 stop 38k
+ 315 ; lda r_prtc ;when prtc.0 is high, not transmit ir.
+ 316 ; ora #c_prtc0_1 ;把PC[1]置高
+ 317 ; sta r_prtc
+ 318 ; ret
+ 319 ;--------------------Play PCM----------------------------------------------
00EE 320 Pcm_Play:
00EE F1 10 321 lda M_sphptr+2
00F0 FC 54 322 sta r_tpp
00F2 F1 0F 323 lda M_sphptr+1
00F4 FC 02 324 sta r_tph
00F6 F1 0E 325 lda M_sphptr
00F8 FC 01 326 sta r_tpl
00FA 1F 327 inca
00FB FD 0E 328 sta M_sphptr
00FD F3 00 329 lda #00h
00FF 99 0F 330 addc M_sphptr+1
0101 FD 0F 331 sta M_sphptr+1
0103 F3 00 332 lda #00h
0105 99 10 333 addc M_sphptr+2
0107 FD 10 334 sta M_sphptr+2
+ 335 ;//20040630,since the rom size is smaller than 64k, as for 89c21,the following code is redundancy
+ 336 ;loop_rom_ready:
+ 337 ; lda r_op1 ;if data rom grand than 64k
+ 338 ; anda #10000000b ;program must detect OP1[7]
+ 339 ; brz loop_rom_ready ;or add 5us delay in program
0109 F8 340 ldv
010A EB FF 341 xora #0xFF
010C 06 01 14 342 brz 10$
010F EB FF 343 xora #0xFF
0111 FD 12 344 sta M_pcmdata
0113 24 345 ret
+ 346 10$:
0114 F3 FF 347 lda #0xFF
0116 FD 11 348 sta M_stopbit
0118 349 play_over:
+ 350 ;call tail
+ 351 ; lda #00h
+ 352 ; sta r_voc ;close PWM and D/A
0118 24 353 ret
+ 354 ;----------------------------------------------------------------;
+ 355 ;Motor Control Pulse Subroutine
+ 356 ;Motor 1 driver circuit controlled by the input1,input2.
+ 357 ;Motor 2 driver circuit controlled by the input3,input4.
+ 358 ;Motor1: input1-----PRTD.3 Motor2: input3-----PRTD.5
+ 359 ; input2-----PRTD.4 input4-----PRTD.6
+ 360 ;----------------------------------------------------------------;
0119 361 motor_control_pulse::
0119 F1 03 362 lda cnt_timer1
011B 1F 363 inca
011C FD 03 364 sta cnt_timer1
011E A5 00 365 cmpe m_ctrl_t1 ;这寄存器在查表中得到
0120 06 01 29 366 brz ctrl_pulse_1st_part
0123 A5 00 367 cmpe m_ctrl_t2
0125 06 01 32 368 brz ctrl_pulse_2nd_part
0128 24 369 ret
0129 370 ctrl_pulse_1st_part: ;
0129 F0 32 371 lda r_prtd
012B D9 00 372 ora m_prtd_ctrl_1_1 ;不理解为什么这样做(是输出高电平吗？但好象****）
012D FC 32 373 sta r_prtd ;PWM valid levels are finished,will output all to high(the 2cnd level)
012F 02 01 5F 374 br motor_ctrl_pulse_end
0132 375 ctrl_pulse_2nd_part:
0132 F0 32 376 lda r_prtd
0134 C9 00 377 anda m_prtd_ctrl_2_0
0136 D9 00 378 ora m_prtd_ctrl_2_1
0138 FC 32 379 sta r_prtd
013A F3 00 380 lda #00h
013C FD 03 381 sta cnt_timer1
+ 382 ;adda #00h ;clear c
013E F1 04 383 lda cnt_ctrl_pulse ;时间长度计数
0140 1F 384 inca
0141 FD 04 385 sta cnt_ctrl_pulse
0143 F1 05 386 lda cnt_ctrl_pulse+1
0145 9B 00 387 addc #00h
0147 FD 05 388 sta cnt_ctrl_pulse+1
0149 A5 01 389 cmpe m_ctrl_pulse+1 ;counter's high 8bit compare with the set value
014B 07 01 5F 390 brnz motor_ctrl_pulse_end ;if it is lower than the set value, go on counting.
014E F1 04 391 lda cnt_ctrl_pulse
0150 A5 00 392 cmpe m_ctrl_pulse ;counter's low 8bit compare with the set vlaue
0152 07 01 5F 393 brnz motor_ctrl_pulse_end ;if it is lower than the set value, go on counting.
0155 F3 00 394 lda #00h ;/*04-02-19*/
0157 FD 04 395 sta cnt_ctrl_pulse
0159 FD 05 396 sta cnt_ctrl_pulse+1
015B F3 01 397 lda #1
015D FD 00 398 sta flg_new_random
015F 399 motor_ctrl_pulse_end:
015F 24 400 ret
+ 401
+
+Symbol Table
+
+ 1 M_pcmdata 0012 GR
+ 1 M_sphptr 000E GR
+ 1 M_stopbit 0011 GR
+ 2 Pcm_Play 00EE R
+ c_ir_group = 000C
+ c_ir_transmit = 0005
+ c_ir_transmit_h = 000D
+ c_ir_transmit_l = 0005
+ c_ir_tx_data = 000F
+ c_prtc0_0 = 00FE
+ c_prtc0_1 = 0001
+ c_prtd012_1 = 0007
+ c_prtd0_1 = 0001
+ c_prtd1_1 = 0002
+ c_prtd2_1 = 0004
+ 1 cnt_ctrl_pulse 0004 GR
+ 1 cnt_ir_rcv 0007 GR
+ cnt_ir_rcv_max = 001D
+ 1 cnt_ir_transmit 0006 GR
+ cnt_ir_transmit_high = 0004
+ 1 cnt_ir_tx_data 000C GR
+ cnt_ir_tx_data_0 = 0004
+ cnt_ir_tx_data_1 = 000C
+ cnt_ir_tx_lead = 0014
+ cnt_ir_tx_stop = 0004
+ 1 cnt_timer1 0003 GR
+ 2 ctrl_pulse_1st_part 0129 R
+ 2 ctrl_pulse_2nd_part 0132 R
+ 1 flg_ir_judge 0008 GR
+ 1 flg_ir_transmit 0009 GR
+ 1 flg_ir_transmit_high 000B GR
+ 1 flg_ir_tx_1 000D GR
+ flg_new_random **** GX
+ 2 ir_transmit 0040 R
+ 2 ir_transmit_data_1 00B4 R
+ 2 ir_transmit_data_low 009A R
+ 2 ir_transmit_low 0081 R
+ 2 ir_transmit_low_00 00C2 R
+ 2 ir_transmit_next_bit 0054 R
+ 2 ir_transmit_over 007A R
+ 2 ir_tx_data_low_over 00D1 R
+ 2 ir_tx_end 00DF R
+ m_ctrl_pulse **** GX
+ m_ctrl_t1 **** GX
+ m_ctrl_t2 **** GX
+ m_prtd_ctrl_1_1 **** GX
+ m_prtd_ctrl_2_0 **** GX
+ m_prtd_ctrl_2_1 **** GX
+ 2 motor_control_pulse 0119 GR
+ 2 motor_ctrl_pulse_end 015F R
+ 2 p_skip_tx 0017 R
+ 2 play_over 0118 R
+ status_ir_rcv **** GX
+ 1 status_ir_transmit 000A GR
+ 2 t1_isr 0000 GR
+ 2 t1_isr_end 0035 R
+ 2 t1_isr_play 0027 R
+ 1 temp_a_1 0000 GR
+ 1 temp_dp_1 0002 GR
+ 1 temp_op1_1 0001 GR
+
+
+Area Table
+
+ 0 . size 0 flags 0
+ 1 time1_var size 13 flags 2
+ 2 timer1_isr size 160 flags 1
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