📄 s3c44b0x.s
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str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerWDT ;HANDLER HandleWDT
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleWDT
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerBDMA1 ;HANDLER HandleBDMA1
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleBDMA1
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerBDMA0 ;HANDLER HandleBDMA0
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleBDMA0
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerZDMA1 ;HANDLER HandleZDMA1
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleZDMA1
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerZDMA0 ;HANDLER HandleZDMA0
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleZDMA0
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerTICK ;HANDLER HandleTICK
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleTICK
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerEINT4567 ;HANDLER HandleEINT4567
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleEINT4567
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerEINT3 ;HANDLER HandleEINT3
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleEINT3
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerEINT2 ;HANDLER HandleEINT2
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleEINT2
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerEINT1 ;HANDLER HandleEINT1
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleEINT1
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
HandlerEINT0 ;HANDLER HandleEINT0
sub sp, sp,#4 ;reserved for PC
stmfd sp!,{r8-r9}
ldr r8, =HandleEINT0
ldr r9, [r8 ]
str r9,[sp,#8]
ldmfd sp!,{r8-r9,pc}
IsrIRQ ;/* using I_ISPR register. */
sub sp, sp, #4 ;/* reserved for PC */
stmfd sp!, {r8-r9}
;# if I_ISPC isn't used properly, I_ISPR can be 0 in this routine.
ldr r9, =I_ISPR
ldr r9, [r9]
cmp r9, #0x0 ;/* If the IDLE mode work-around is used, r9 may be 0 sometimes. */
beq l2
mov r8, #0x0
l0
movs r9, r9, lsr #1
bcs l1
add r8, r8, #4
b l0
l1
ldr r9, =HandleADC
add r9, r9, r8
ldr r9, [r9]
str r9, [sp,#8]
ldmfd sp!, {r8-r9,pc}
l2
ldmfd sp!, {r8-r9}
add sp, sp, #4
;# subs pc, lr, #4
; mov pc, lr
; CPU Wrapper and Bus Priorities Configuration
IF SYS_SETUP <> 0
SYS_CFG
DCD CPUW_BASE
DCD BUSP_BASE
DCD SYSCFG_Val
DCD NCACHBE0_Val
DCD NCACHBE1_Val
DCD SBUSCON_Val
ENDIF
; Memory Controller Configuration
IF MC_SETUP <> 0
MC_CFG
DCD BWSCON_Val
DCD BANKCON0_Val
DCD BANKCON1_Val
DCD BANKCON2_Val
DCD BANKCON3_Val
DCD BANKCON4_Val
DCD BANKCON5_Val
DCD BANKCON6_Val
DCD BANKCON7_Val
DCD REFRESH_Val
DCD BANKSIZE_Val
DCD MRSRB6_Val
DCD MRSRB7_Val
ENDIF
; Clock Management Configuration
IF CLK_SETUP <> 0
CLK_CFG
DCD CLK_BASE
DCD PLLCON_Val
DCD CLKCON_Val
DCD CLKSLOW_Val
DCD LOCKTIME_Val
ENDIF
; I/O Configuration
IF PIO_SETUP <> 0
PIO_CFG
DCD PCONA_Val
DCD PCONB_Val
DCD PCONC_Val
DCD PCOND_Val
DCD PCONE_Val
DCD PCONF_Val
DCD PCONG_Val
DCD PUPC_Val
DCD PUPD_Val
DCD PUPE_Val
DCD PUPF_Val
DCD PUPG_Val
DCD SPUCR_Val
ENDIF
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
IF WT_SETUP <> 0
LDR R0, =WT_BASE
LDR R1, =WTCON_Val
LDR R2, =WTDAT_Val
STR R2, [R0, #WTCNT_OFS]
STR R2, [R0, #WTDAT_OFS]
STR R1, [R0, #WTCON_OFS]
ENDIF
IF CLK_SETUP <> 0
ADR R8, CLK_CFG
LDMIA R8, {R0-R4}
STR R4, [R0, #LOCKTIME_OFS]
STR R1, [R0, #PLLCON_OFS]
STR R3, [R0, #CLKSLOW_OFS]
STR R2, [R0, #CLKCON_OFS]
ENDIF
IF SYS_SETUP <> 0
ADR R8, SYS_CFG
LDMIA R8, {R0-R5}
STMIA R0, {R2-R4}
STR R5, [R1]
ENDIF
IF VIM_SETUP <> 0
ldr r0, =HandleIRQ
ldr r1, =IsrIRQ
str r1, [r0]
ENDIF
IF MC_SETUP <> 0
ADR R13, MC_CFG
LDMIA R13, {R0-R12}
LDR R13, =MC_BASE
STMIA R13, {R0-R12}
ENDIF
IF PIO_SETUP <> 0
ADR R13, PIO_CFG
LDMIA R13, {R0-R12}
LDR R13, =PIO_BASE
IF PIOA_SETUP <> 0
STR R0, [R13, #PCONA_OFS]
ENDIF
IF PIOB_SETUP <> 0
STR R1, [R13, #PCONB_OFS]
ENDIF
IF PIOC_SETUP <> 0
STR R2, [R13, #PCONC_OFS]
STR R7, [R13, #PUPC_OFS]
ENDIF
IF PIOD_SETUP <> 0
STR R3, [R13, #PCOND_OFS]
STR R8, [R13, #PUPD_OFS]
ENDIF
IF PIOE_SETUP <> 0
STR R4, [R13, #PCONE_OFS]
STR R9, [R13, #PUPE_OFS]
ENDIF
IF PIOF_SETUP <> 0
STR R5, [R13, #PCONF_OFS]
STR R10,[R13, #PUPF_OFS]
ENDIF
IF PIOG_SETUP <> 0
STR R6, [R13, #PCONG_OFS]
STR R11,[R13, #PUPG_OFS]
ENDIF
IF PSPU_SETUP <> 0
STR R12,[R13, #SPUCR_OFS]
ENDIF
ENDIF
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF :DEF:__MICROLIB
EXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
ENDIF
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END
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