motfccend.c

motorola 8260 CPU上面

					        obtain memory\n"),
					        1, 2, 3, 4, 5, 6);
		return (ERROR);
		}

	    /* store the pointer to the clBlock area and its size */

	    pDrvCtrl->pBufBase = clDescTbl[0].memArea;

	    pDrvCtrl->bufSize = clDescTbl[0].memSize;

	    MOT_FCC_FLAG_SET (MOT_FCC_OWN_BUF_MEM);

	    /* cache functions descriptor for data buffers */

	    motFccBufCacheFuncs.flushRtn = cacheArchFlush;
	    motFccBufCacheFuncs.invalidateRtn = cacheArchInvalidate;
	    motFccBufCacheFuncs.virtToPhysRtn = NULL;
	    motFccBufCacheFuncs.physToVirtRtn = NULL;

	    pDrvCtrl->bufCacheFuncs = motFccBufCacheFuncs;

	    break;

	default :			       /* the user provided an area */

	    if (pDrvCtrl->bufSize == 0) 
		{
		MOT_FCC_LOG (MOT_FCC_DBG_LOAD, ("motFccInitMem: not enough 
					        memory\n"),
					        1, 2, 3, 4, 5, 6);
		return (ERROR);
		}

	    /* 
	     * check the user provided enough memory with reference
	     * to the given number of receive/transmit frames, if any.
	     */

	    if (pDrvCtrl->bufSize < clDescTbl[0].memSize)
		{
		MOT_FCC_LOG (MOT_FCC_DBG_LOAD, ("motFccInitMem: not enough 
					       memory\n"),
					       1, 2, 3, 4, 5, 6);
		return (ERROR);
		}

	    MOT_FCC_FLAG_CLEAR (MOT_FCC_OWN_BUF_MEM);

	    pDrvCtrl->bufCacheFuncs = cacheNullFuncs;

	    break;
	}

    /* zero and align the shared memory */

    memset (pDrvCtrl->pBufBase, 0, (int) pDrvCtrl->bufSize);

    pDrvCtrl->pBufBase = (char *) (((UINT32) (pDrvCtrl->pBufBase) +
                                   CL_ALIGNMENT - 1) &
                                   ~(CL_ALIGNMENT - 1));
 
    /* pool of cluster blocks */

    if (mclBlkConfig.clBlkNum == 0)
	mclBlkConfig.clBlkNum = clDescTbl[0].clNum;

    /* get memory for mblks */

    if (mclBlkConfig.memArea == NULL)
	{
	/* memory size adjusted to hold the netPool pointer at the head */

	mclBlkConfig.memSize = ((mclBlkConfig.mBlkNum
				* (M_BLK_SZ + MBLK_ALIGNMENT))
				+ (mclBlkConfig.clBlkNum
				* (CL_BLK_SZ + CL_ALIGNMENT)));

	mclBlkConfig.memArea = (char *) memalign (MBLK_ALIGNMENT, 
						  mclBlkConfig.memSize);

	if (mclBlkConfig.memArea == NULL)
	    {
	    return (ERROR);
	    }

	/* store the pointer to the mBlock area */

	pDrvCtrl->pMBlkArea = mclBlkConfig.memArea;
	pDrvCtrl->mBlkSize = mclBlkConfig.memSize;
	}

    /* init the mem pool */

    if (netPoolInit (pDrvCtrl->endObj.pNetPool, &mclBlkConfig, 
		     &clDescTbl[0], clDescTblNumEnt, NULL) 
	== ERROR)
	{
	return (ERROR);
	}

    if ((pDrvCtrl->pClPoolId = netClPoolIdGet (pDrvCtrl->endObj.pNetPool,
					       MOT_FCC_MAX_CL_LEN, FALSE)) 
        == NULL)
	{
	return (ERROR);
	}

    MOT_FCC_LOG (MOT_FCC_DBG_LOAD, ("motFccInitMem... Done\n"),
				    0, 0, 0, 0, 0, 0);

    return OK;
    }

/**************************************************************************
*
* motFccStart - start the device
*
* This routine starts the FCC device and brings it up to an operational
* state.  The driver must have already been loaded with the motFccEndLoad()
* routine.
*
* INTERNAL
* The speed field inthe phyInfo structure is only set after the call
* to the physical layer init routine. On the other hand, the mib2 
* interface is initialized in the motFccEndLoad() routine, and the default
* value of 10Mbit assumed there is not always correct. We need to
* correct it here.
*
* RETURNS: OK, or ERROR if the device could not be started.
*
*/
LOCAL STATUS motFccStart
    (
    DRV_CTRL * pDrvCtrl       /* pointer to DRV_CTRL structure */
    )
    {
    int		retVal;		/* convenient holder for return value */
    char        bucket[4];	/* holder for vxMemProbe */

    MOT_FCC_LOG (MOT_FCC_DBG_START, ("Starting end...\n"), 1, 2, 3, 4, 5, 6);

    /* must have been loaded */

    if (!pDrvCtrl->loaded)
	return (ERROR);

    if (vxMemProbe ((char *) (pDrvCtrl->fccIramAddr),
		    VX_READ, 4, &bucket[0]) != OK)
        {
        MOT_FCC_LOG (MOT_FCC_DBG_START,
                   (": need MMU mapping for address 0x%x\n"),
                   (UINT32) pDrvCtrl->fccIramAddr, 2, 3, 4, 5, 6);
	return (ERROR);
        }

    if (motFccTbdInit (pDrvCtrl) == ERROR)
	return (ERROR);

    if (motFccRbdInit (pDrvCtrl) == ERROR)
	return (ERROR);

    /* set some flags to default values */

    pDrvCtrl->txStall = FALSE;
    pDrvCtrl->tbdIndex = 0;
    pDrvCtrl->usedTbdIndex = 0;
    pDrvCtrl->cleanTbdNum = pDrvCtrl->tbdNum;
    pDrvCtrl->rbdIndex = 0;

    /* acknowledge system interrupt */

    SYS_FCC_INT_ACK (pDrvCtrl, retVal);
    if (retVal == ERROR)
	return (ERROR);
	
    /* connect the interrupt handler */

    SYS_FCC_INT_CONNECT (pDrvCtrl, motFccInt, (int) pDrvCtrl, retVal);
    if (retVal == ERROR)
	return (ERROR);

    /* enable system interrupt: set relevant bit in SIMNR_L */

    SYS_FCC_INT_ENABLE (pDrvCtrl, retVal);
    if (retVal == ERROR)
	return (ERROR);
	
    /* call the BSP to do any other initialization (MII interface) */

    SYS_FCC_ENET_ENABLE;

    /* initialize some fields in the PHY info structure */
#if 0 
    if (motFccPhyPreInit (pDrvCtrl) != OK)
	{
	MOT_FCC_LOG (MOT_FCC_DBG_LOAD, ("Failed to pre-initialize the PHY\n"),
					0, 0, 0, 0, 0, 0);
	return (ERROR);
	}

    /* initialize the Physical medium layer */

    if (_func_motFccPhyInit == NULL)
	return (ERROR);

    if (((* _func_motFccPhyInit) (pDrvCtrl->phyInfo)) != OK)
	{
	MOT_FCC_LOG (MOT_FCC_DBG_LOAD, ("Failed to initialize the PHY\n"),
					0, 0, 0, 0, 0, 0);
	return (ERROR);
	}
#endif
    /* initialize the chip */

    if (motFccInit (pDrvCtrl) == ERROR)
	return (ERROR);

    /* correct the speed for the mib2 stuff */

    pDrvCtrl->endObj.mib2Tbl.ifSpeed = pDrvCtrl->phyInfo->phySpeed;

    /* startup the transmitter */

    MOT_FCC_TX_ACTIVATE;

    /* mark the interface as up */

    END_FLAGS_SET (&pDrvCtrl->endObj, (IFF_UP | IFF_RUNNING));

    /* startup the receiver */

    MOT_FCC_RX_ACTIVATE;

    /* Flush the write pipe */

    CACHE_PIPE_FLUSH ();

    MOT_FCC_LOG (MOT_FCC_DBG_START, ("Starting end... Done\n"), 
				     1, 2, 3, 4, 5, 6);

    return (OK);
    }

/**************************************************************************
*
* motFccStop - stop the 'motfec' interface
*
* This routine marks the interface as inactive, disables interrupts and 
* the Ethernet Controller. As a result, reception is stopped immediately,
* and transmission is stopped after a bad CRC is appended to any frame
* currently being transmitted. The reception/transmission control logic
* (FIFO pointers, buffer descriptors, etc.) is reset. To bring the 
* interface back up, motFccStart() must be called.
*
* RETURNS: OK, always.
*/
LOCAL STATUS motFccStop
    (
    DRV_CTRL *  pDrvCtrl       /* pointer to DRV_CTRL structure */
    )
    {
    int		retVal;		/* convenient holder for return value */
    UINT8	command = 0;			/* command to issue to the CP */

    MOT_FCC_LOG (MOT_FCC_DBG_LOAD, ("motFccStop...\n"), 1, 2, 3, 4, 5, 6);

    /* mark the interface as down */

    END_FLAGS_CLR (&pDrvCtrl->endObj, (IFF_UP | IFF_RUNNING));

    /* issue a graceful stop transmit command to the CP */

    command = M8260_CPCR_TX_GRSTOP;
    if (motFccCpcrCommand (pDrvCtrl, command) == ERROR)
	return (ERROR);

    /* wait for the related interrupt */

    MOT_FCC_GRA_SEM_TAKE;

    /* mask chip interrupts */

    MOT_FCC_INT_DISABLE;	  

    /* disable system interrupt: reset relevant bit in SIMNR_L */

    SYS_FCC_INT_DISABLE (pDrvCtrl, retVal);
    if (retVal == ERROR)
	return (ERROR);

    /* disconnect the interrupt handler */

    SYS_FCC_INT_DISCONNECT (pDrvCtrl, motFccInt, (int)pDrvCtrl, retVal);
    if (retVal == ERROR)
	return (ERROR);

    /* call the BSP to disable the MII interface */

    SYS_FCC_ENET_DISABLE;

    /* free buffer descriptors */

    if (motFccBdFree (pDrvCtrl) != OK)
	return (ERROR);

    MOT_FCC_LOG (MOT_FCC_DBG_LOAD, ("motFccStop... Done \n"), 
				    1, 2, 3, 4, 5, 6);

    return OK;
    } 

/*******************************************************************************
* motFccInt - entry point for handling interrupts from the FCC
*
* The interrupting events are acknowledged to the device, so that the device
* will de-assert its interrupt signal.  The amount of work done here is kept
* to a minimum; the bulk of the work is deferred to the netTask.
*
* RETURNS: N/A
*/
LOCAL void motFccInt
    (
    DRV_CTRL *  pDrvCtrl       /* pointer to DRV_CTRL structure */
    )
    {
    UINT16	event = 0;	/* event intr register */
    UINT16	mask = 0;	/* holder for the mask intr register */
    UINT16	status;		/* status word */
    UINT32	fccIramAddr = pDrvCtrl->fccIramAddr;	/* a convenience */

    CACHE_PIPE_FLUSH ();

    /* read and save the interrupt event register */

    MOT_FCC_REG_WORD_RD (fccIramAddr + M8260_FCC_FCCER_OFF,
			 event);

    /* clear all events */

    MOT_FCC_REG_WORD_WR (fccIramAddr + M8260_FCC_FCCER_OFF,
			 event & M8260_FEM_ETH_EVENT);

    CACHE_PIPE_FLUSH ();

    /* read the interrupt mask register */

    MOT_FCC_REG_WORD_RD (fccIramAddr + M8260_FCC_FCCMR_OFF,
			 mask);

    /* read status word again */

    MOT_FCC_REG_WORD_RD (fccIramAddr + M8260_FCC_FCCER_OFF,
			 status);

    MOT_FCC_LOG (MOT_FCC_DBG_INT, ("motFccInt: event 0x%x, status 0x%x
				    mask=0x%x \n"), 
				   (event & M8260_FEM_ETH_EVENT), status, 
				   mask, 0, 0, 0);

    /* handle tx error interrupts */

    if ((event & M8260_FEM_ETH_TXE) == M8260_FEM_ETH_TXE)
	{
	MOT_FCC_TX_ERR_ADD;
	MOT_FCC_LOG (MOT_FCC_DBG_INT, ("motFccInt: tx error\n"),
				       0, 0, 0, 0, 0, 0);
	/* stop and restart the device */

	(void) netJobAdd ((FUNCPTR) motFccStop, (int) pDrvCtrl,
			  event, 0, 0, 0);
	(void) netJobAdd ((FUNCPTR) motFccStart, (int) pDrvCtrl,
			  event, 0, 0, 0);
	}

    /* handle receive error interrupts */

    if ((event & M8260_FEM_ETH_BSY) == M8260_FEM_ETH_BSY)
	{
	MOT_FCC_RX_BSY_ADD;

	MOT_FCC_LOG (MOT_FCC_DBG_INT, ("motFccInt: rx error\n"),
				       0, 0, 0, 0, 0, 0);
	}

    /* handle transmit and receive interrupts */

    if ((((event & M8260_FEM_ETH_TXB) == M8260_FEM_ETH_TXB) 
	&& ((mask & M8260_FEM_ETH_TXB) == M8260_FEM_ETH_TXB)) ||
	(((event & M8260_FEM_ETH_RXF) == M8260_FEM_ETH_RXF) 
	&& ((mask & M8260