pspan.h

motorola 8260 CPU上面

 */

#define PCI_HS_CSR_INS      0x00800000  /* ENUM# Status - Insertion */
#define PCI_HS_CSR_EXT      0x00400000  /* ENUM# Status - Extraction */
#define PCI_HS_CSR_LOO      0x00080000  /* LED ON/OFF */
#define PCI_HS_CSR_EIM      0x00020000  /* ENUM# Signal Mask */
#define PCI_HS_CSR_NXT_PTR  0x0000FF00  /* Next Pointer */
#define PCI_HS_CSR_CAP_ID   0x000000FF  /* Capability ID */

/*
 * PCI Vital Product Data Capability Register
 */

#define PCI_VPDC_F          0x80000000  /* Data Transfer Complete Flag */
#define PCI_VPDC_VPDA       0x00FF0000  /* Vital Product Data Address */
#define PCI_VPDC_NXT_PTR    0x0000FF00  /* Next Pointer */
#define PCI_VPDC_CAP_ID     0x000000FF  /* Capability ID */

/*
 * PCI Target Image Control Register
 */

#define PCI_TI_CTL_IMG_EN 0x80000000  /* Image Enable */
#define PCI_TI_CTL_TA_EN  0x40000000  /* Translation Address Enable */
#define PCI_TI_CTL_BAR_EN 0x20000000  /* PCI Base Address Register Enable */
#define PCI_TI_CTL_MD_EN  0x10000000  /* Master Decode Enable */
#define PCI_TI_CTL_BS     0x0F000000  /* Block Size */
#define PCI_TI_CTL_MODE   0x00800000  /* Image Mode */
#define PCI_TI_CTL_DEST   0x00400000  /* Destination Bus */
#define PCI_TI_CTL_RTT    0x001F0000  /* Processsor Bus Read Transfer Type */
#define PCI_TI_CTL_GBL_   0x00008000  /* Global */
#define PCI_TI_CTL_CI_    0x00004000  /* Cache Inhibit */
#define PCI_TI_CTL_WTT    0x00001F00  /* Processor Bus Write Transfer Type */
#define PCI_TI_CTL_PRKEEP 0x00000080  /* Prefetch Read Keep Data */
#define PCI_TI_CTL_END    0x00000060  /* Endian Conversion Mode */
#define PCI_TI_CTL_MRA    0x00000010  /* PCI Memory Read Alias to 
                                                Memory Read Multiple */
#define PCI_TI_CTL_RD_AMT 0x00000007  /* Prefetch Size */

/*
 * PCI Target Image Translation Address Register
 */

#define PCI_TI_TADDR_TADDR  0xFFFF0000  /* Translation Address */
#define PCI_TI_TADDR_M7     0x00000080  /* Master Select 7 */
#define PCI_TI_TADDR_M6     0x00000040  /* Master Select 6 */
#define PCI_TI_TADDR_M5     0x00000020  /* Master Select 5 */
#define PCI_TI_TADDR_M4     0x00000010  /* Master Select 4 */
#define PCI_TI_TADDR_M3     0x00000008  /* Master Select 3 */
#define PCI_TI_TADDR_M2     0x00000004  /* Master Select 2 */
#define PCI_TI_TADDR_M1     0x00000002  /* Master Select 1 */

/*
 * PCIx to PCIy Configuration Cycle Information Register
 */

#define PCI_CONF_INFO_BUS_NUM   0x00FF0000  /* Bus Number */
#define PCI_CONF_INFO_DEV_NUM   0x00007800  /* Device Number */
#define PCI_CONF_INFO_FUNC_NUM  0x00000700  /* Function Number */
#define PCI_CONF_INFO_REG_NUM   0x000000FC  /* Register Offset */
#define PCI_CONF_INFO_TYPE      0x00000001  /* Configuration Cycle Type */

/*
 * PCI Bus Error Control and Status Register
 */

#define PCI_ERRCS_MES       0x02000000    /* Multiple Error Status */
#define PCI_ERRCS_ES        0x01000000    /* Error Status */
#define PCI_ERRCS_CMDERR    0x000000F0    /* PCI Command Error Log */

/*
 * PCI Miscellaneous Control and Status Register
 */

#define PCI_MISC_CSR_BSREG_BAR_EN 0x00008000  /* PCI Registers Image Base
                                                  Address Register Enable */
#define PCI_MISC_CSR_MAX_RETRY    0x00000F00  /* Maximum number of PCI Retry
                                                  Terminations */
#define PCI_MISC_CSR_MAC_ERR      0x00000080  /* Master Abort Configuration
                                                  Error Mapping */

/*
 * PCI Bus Arbiter Control Register
 */

#define PCI_ARB_CTRL_M7       0x00008000  /* Arbitration Level 
                                              for PCI Master Device 7 */
#define PCI_ARB_CTRL_M6       0x00004000  /* Arbitration Level
                                              for PCI Master Device 6 */
#define PCI_ARB_CTRL_M5       0x00002000  /* Arbitration Level
                                              for PCI Master Device 5 */
#define PCI_ARB_CTRL_M4       0x00001000  /* Arbitration Level
                                              for PCI Master Device 4 */
#define PCI_ARB_CTRL_M3       0x00000800  /* Arbitration Level
                                              for PCI Master Device 3 */
#define PCI_ARB_CTRL_M2       0x00000400  /* Arbitration Level
                                              for PCI Master Device 2 */
#define PCI_ARB_CTRL_M1       0x00000200  /* Arbitration Level
                                              for PCI Master Device 1 */
#define PCI_ARB_CTRL_PS       0x00000100  /* Arbitration Level
                                              for PSpan */
#define PCI_ARB_CTRL_PARK     0x00000008  /* PCI Bus Parking Algorithm */
#define PCI_ARB_CTRL_BM_PARK  0x00000007  /* Parked Master */

/*
 * Processor Bus Slave Image Control Register
 */

#define PB_SI_CTL_IMG_EN  0x80000000  /* Image Enable */
#define PB_SI_CTL_TA_EN   0x40000000  /* Translation Address Enable */
#define PB_SI_CTL_BS      0x1F000000  /* Block Size */
#define PB_SI_CTL_MODE    0x00800000  /* Image Mode */
#define PB_SI_CTL_DEST    0x00400000  /* Destination Bus */
#define PB_SI_CTL_PRKEEP  0x00000080  /* Prefetch Read Keep */
#define PB_SI_CTL_END     0x00000060  /* Endian Conversion Mode */
#define PB_SI_CTL_RD_AMT  0x00000007  /* Read Prefetch Amount */

/*
 * Processor Bus Slave Image Translation Address Register
 */

#define PB_SI_TADDR_TADDR 0xFFFFF000  /* Translation Address */
#define PB_SI_TADDR_M3    0x00000008  /* Master Select 3 */
#define PB_SI_TADDR_M2    0x00000004  /* Master Select 2 */
#define PB_SI_TADDR_M1    0x00000002  /* Master Select 1 */

/*
 * Processor Bus Slave Image Base Address Register
 */

#define PB_SI_BADDR_BA    0xFFFFF000  /* Processor Bus Base Address */

/*
 * Processor Bus Register Image Base Address Register
 */

#define PB_REG_BADDR_BA   0xFFFFF000  /* PB Register Base Address */
#define PB_REG_BADDR_END  0x00000001  /* Endian Conversion Mode */

/*
 * Processor Bus PCI Configuration Cycle Information Register
 */

#define PB_CONF_INFO_DEST     0x01000000  /* Destination Bus */
#define PB_CONF_INFO_BUS_NUM  0x00FF0000  /* Bus Number */
#define PB_CONF_INFO_DEV_NUM  0x00007800  /* Device Number */
#define PB_CONF_INFO_FUNC_NUM 0x00000700  /* Function Number */
#define PB_CONF_INFO_REG_NUM  0x000000FC  /* Register Number */
#define PB_CONF_INFO_TYPE     0x00000001  /* Configuration Cycle Type */

/*
 * Processor Bus Error Control and Status Register
 */

#define PB_ERRCS_MES          0x02000000  /* Multiple Error Status */
#define PB_ERRCS_ES           0x01000000  /* Error Status */
#define PB_ERRCS_TT_ERR       0x0000F800  /* PB Transaction Type Error Log */
#define PB_ERRCS_SIZ_ERR      0x000000F0  /* PB SIZ field Error Log */

/*
 * Processor Bus Miscellaneous Control and Status Register
 */

#define PB_MISC_CSR_MAX_RETRY 0x00000F00  /* Maximum Number of Retries */
#define PB_MISC_CSR_EXTCYC    0x00000080  /* Extended Cycles */
#define PB_MISC_CSR_MAC_TEA   0x00000040  /* Master Abort Configuration
                                              Error Mapping */
#define PB_MISC_CSR_TEA_EN    0x00000010  /* Suppress PB_TEA generation */
#define PB_MISC_CSR_TT_ERR_EN 0x00000008  /* Transfer Type Err TEA_ Enable */
#define PB_MISC_CSR_DP_EN     0x00000004  /* Data Parity Enable */
#define PB_MISC_CSR_AP_EN     0x00000002  /* Address Parity Enable */
#define PB_MISC_CSR_PARITY    0x00000001  /* Parity */

/*
 * Processor Bus Arbiter Control Register
 */

#define PB_ARB_CTRL_M3_EN   0x00080000  /* External Master 3 Enable */
#define PB_ARB_CTRL_M2_EN   0x00040000  /* External Master 2 Enable */
#define PB_ARB_CTRL_M1_EN   0x00020000  /* External Master 1 Enable */
#define PB_ARB_CTRL_M3_PRI  0x00000800  /* External Master 3 Priority Level */
#define PB_ARB_CTRL_M2_PRI  0x00000400  /* External Master 2 Priority Level */
#define PB_ARB_CTRL_M1_PRI  0x00000200  /* External Master 1 Priority Level */
#define PB_ARB_CTRL_PS_PRI  0x00000100  /* PowerSpan Priority Level */
#define PB_ARB_CTRL_PARK    0x00000004  /* Bus Park Mode */
#define PB_ARB_CTRL_BM_PARK 0x00000003  /* Bus Master to be Parked */

/*
 * DMA Destination Address Register
 */

#define DMA_DST_ADDR_DADDR  0xFFFFFFF8  /* Starting Byte Address on 
                                            the Destination Bus */

/*
 * DMA Transfer Control Register
 */

#define DMA_TCR_SRC_PORT  0xC0000000  /* Source Port for DMA transfer */
#define DMA_TCR_DST_PORT  0x03000000  /* Destination Port for DMA transfer */
#define DMA_TCR_END       0x00C00000  /* Endian Conversion Mode */
#define DMA_TCR_BC        0x00FFFFFF  /* Byte Count */

/*
 * DMA Command Packet Pointer Register
 */

#define DMA_CPP_NCP       0xFFFFFFE0  /* Next Command Packet Address */
#define DMA_CPP_LAST      0x00000001  /* Last Item */

/*
 * DMA General Control and Status Register
 */

#define DMA_GCSR_GO         0x80000000  /* DMA Go Bit */
#define DMA_GCSR_CHAIN      0x40000000  /* DMA Chaining */
#define DMA_GCSR_STOP_REQ   0x04000000  /* DMA Stop Request */
#define DMA_GCSR_HALT_REQ   0x02000000  /* DMA Halt Request */
#define DMA_GCSR_DACT       0x00800000  /* DMA Active */
#define DMA_GCSR_OFF        0x00070000  /* DMA Channel Off Counter */
#define DMA_GCSR_P1_ERR     0x00002000  /* PCI 1 Bus Error */
#define DMA_GCSR_P2_ERR     0x00001000  /* PCI 2 Bus Error */
#define DMA_GCSR_PB_ERR     0x00000800  /* Processor Bus Error */
#define DMA_GCSR_STOP       0x00000400  /* DMA Stopped Flag */
#define DMA_GCSR_HALT       0x00000200  /* DMA Halted Flag */
#define DMA_GCSR_DONE       0x00000100  /* DMA Done Flag */
#define DMA_GCSR_P1_ERR_EN  0x00000020  /* Primary PCI Error
                                                Interrupt Enable */
#define DMA_GCSR_P2_ERR_EN  0x00000010  /* Secondary PCI Error
                                                Interrupt Enable */
#define DMA_GCSR_PB_ERR_EN  0x00000008  /* Processor Bus Error
                                                Interrupt Enable */
#define DMA_GCSR_STOP_EN    0x00000004  /* DMA Stop Interrupt Enable */
#define DMA_GCSR_HALT_EN    0x00000002  /* DMA Halt Interrupt Enable */
#define DMA_GCSR_DONE_EN    0x00000001  /* DMA Done Interrupt Enable */

/*
 * DMA Attributes Register
 */

#define DMA_ATTR_CP_PORT  0xC0000000  /* Command Packet Port */
#define DMA_ATTR_GBL_     0x10000000  /* Processor Bus Global */
#define DMA_ATTR_CI_      0x08000000  /* Processor Bus Cache Inhibit */
#define DMA_ATTR_RTT      0x001F0000  /* Processor Bus Read Transfer Type */
#define DMA_ATTR_WTT      0x00001F00  /* Processor Bus Write Transfer Type */

/*
 * Miscellaneous Control and Status Register
 */

#define MISC_CSR_TUNDRA_DEV_ID  0xFF000000  /* Tundra Internal Device ID */
#define MISC_CSR_TUNDRA_VER_ID  0x00FF0000  /* Tundra Internal Version ID */
#define MISC_CSR_VPD_EN         0x00008000  /* PCI Vital Product Data */
#define MISC_CSR_VPD_CS         0x00007000  /* PCI Vital Product Data 
                                                      EEPROM Chip Select */
#define MISC_CSR_ELOAD_OPT      0x00000100  /* EEPROM Load Option */
#define MISC_CSR_P1_LOCKOUT     0x00000080  /* P1 Lockout */
#define MISC_CSR_P2_LOCKOUT     0x00000040  /* P2 Lockout */
#define MISC_CSR_PCI_ARB_CFG    0x00000008  /* PCI Arbiter Pins Configured */
#define MISC_CSR_PCI_M7         0x00000004  /* PCI Arbiter Master 7 */
#define MISC_CSR_PCI_M6         0x00000002  /* PCI Arbiter Master 6 */
#define MISC_CSR_PCI_M5         0x00000001  /* PCI Arbiter Master 5 */

/*
 * Clock Control Register
 */

#define CLOCK_CTL_PB_TUNE 0xFF000000  /* PB PLL Tune Bits */
#define CLOCK_CTL_P1_TUNE 0x00FF0000  /* P1 PLL Tune Bits */
#define CLOCK_CTL_P2_TUNE 0x0000FF00  /* P2 PLL Tune Bits */

/*
 * I2C Interface Control and Status Register
 */

#define I2C_CSR_ADDR      0xFF000000  /* Specifies I2C Device Address
                                                        to be Accessed */
#define I2C_CSR_DATA      0x00FF0000  /* Specifies the Required Data
                                                        for a Write */
#define I2C_CSR_DEV_CODE  0x0000F000  /* Device Select.
                                                  I2C 4-bit Device Code */
#define I2C_CSR_CS        0x00000E00  /* Chip Select */
#define I2C_CSR_RW        0x00000100  /* Read/Write */
#define I2C_CSR_ACT       0x00000080  /* I2C Interface Active */
#define I2C_CSR_ERR       0x00000040  /* Error */

/*
 * Reset Control and Status Register
 */

#define RST_CSR_PB_RST_DIR    0x80000000  /* Status of PB_RST_DIR pin */
#define RST_CSR_PB_ARB_EN     0x40000000  /* Processor Bus Arbiter Enable */
#define RST_CSR_PB_FAST       0x20000000  /* PB Clock Frequency Selection */
#define RST_CSR_PCI_BOOT      0x10000000  /* PCI Boot */
#define RST_CSR_CONFIG_SLAVE  0x08000000  /* Configuration Slave */
#define RST_CSR_P1_RST_DIR    0x00800000  /* Status of P1_RST_DIR Pin */
#define RST_CSR_P1_ARB_EN     0x00400000  /* P1 Arbiter Enable */
#define RST_CSR_P1_M66EN      0x00200000  /* P1 Clock Frequency Selection */
#define RST_CSR_P1_R64_EN     0x00020000  /* P1 REQ64_ Output Enable */
#define RST_CSR_P1_D64        0x00010000  /* P1 Databus Width */
#define RST_CSR_P2_RST_DIR    0x00008000  /* Status of P2_RST_DIR pin */
#define RST_CSR_P2_ARB_EN     0x00004000  /* P2 Arbiter Enable */
#define RST_CSR_P2_M66EN      0x00002000  /* P2 Clock Frequency Selection */
#define RST_CSR_PRI_PCI       0x00000100  /* Designated Primary PCI Bus */
#define RST_CSR_DEBUG_EN      0x00000040  /* Debug Mode Enable */
#define RST_CSR_BYPASS_EN     0x00000020  /* PLL Bypass Enable */
#define RST_CSR_ELOAD         0x00000010  /* EEPROM Load After Reset */
#define RST_CSR_I20_CTRL      0x00000008  /* I2O Controller */
#define RST_CSR_TMODE         0x00000007  /* Test Mode */

/*
 * Interrupt Status Register 0
 * Interrupt Enable Register 0
 */

#define IR0_ISR1_ACTV   0x80000000  /* Interrupt Status Bit is set in
                                                    the ISR1 Register */
#define IR0_I20_HOST    0x20000000  /* Outbound Post List FIFO not empty */
#define IR0_I20_IOP     0x10000000  /* Inbound Post List FIFO not empty */
#define IR0_DMA3        0x08000000  /* Set When DMA3 Generates an Interrupt */
#define IR0_DMA2        0x04000000  /* Set When DMA2 Generates an Interrupt */
#define IR0_DMA1        0x02000000  /* Set When DMA1 Generates an Interrupt */
#define IR0_DMA0        0x01000000  /* Set When DMA0 Generates an Interrupt */
#define IR0_P2_HW       0x00800000  /* PCI 2 Hardware Interrupt */
#define IR0_P1_HW       0x00400000  /* PCI 1 Hardware Interrupt */
#define IR0_INT5_HW     0x00200000  /* Hardware Interrupt on INT[5] Pin */
#define IR0_INT4_HW     0x00100000  /* Hardware Interrupt on INT[4] Pin */
#define IR0_INT3_HW     0x00080000  /* Hardware Interrupt on INT[3] Pin */
#define IR0_INT2_HW     0x00040000  /* Hardware Interrupt on INT[2] Pin */
#define IR0_INT1_HW     0x00020000  /* Hardware Interrupt on INT[1] Pin */
#define IR0_INT0_HW     0x00010000  /* Hardware Interrupt on INT[0] Pin */
#define IR0_DB7         0x00008000  /* Doorbell Reg 7 Written to in IER Reg */
#define IR0_DB6         0x00004000  /* Doorbell Reg 6 Written to in IER Reg */
#define IR0_DB5         0x00002000  /* Doorbell Reg 5 Written to in IER Reg */
#define IR0_DB4         0x00001000  /* Doorbell Reg 4 Written to in IER Reg */
#define IR0_DB3         0x00000800  /* Doorbell Reg 3 Written to in IER Reg */
#define IR0_DB2         0x00000400  /* Doorbell Reg 2 Written to in IER Reg */