📄 pspanlib.c
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* bs 5 bit block size
* rd_amt 3 bit read amount
*
* (refer to the PowerSpan Registers Spec for descriptions of the bs
* and rd_amt fields)
*
* Description:
* Setup PCI Target Images - Minimum setup to enable to PCI target image.
* Defaults: LE (no swap), Dest=PB
* If baddr is 0, then the base address register is not programmed and the
* existing address will be used (for Coppermine, the host OS sets the
* base address registers on P1).
*
* Return Value: SUCCESS/FAILURE
*
=========================================================================*/
UINT32 PspanPciTargetImageSetup
(
PPSPAN pspan,
UINT32 bus,
UINT32 img_num,
UINT32 baddr,
UINT32 taddr,
UINT32 bs,
UINT32 rd_amt
)
{
UINT32 retval;
VUINT32 pci_tix_ctl_write_val;
UINT32 temp;
VUINT32 *pci_tix_ctl_ptr = NULL;
VUINT32 *pci_tix_baddr_ptr = NULL;
VUINT32 *pci_tix_taddr_ptr = NULL;
retval = SUCCESS;
pci_tix_ctl_write_val = 0L;
pci_tix_ctl_write_val = pci_tix_ctl_write_val | PCI_TI_CTL_IMG_EN;
pci_tix_ctl_write_val = pci_tix_ctl_write_val | PCI_TI_CTL_TA_EN;
pci_tix_ctl_write_val = pci_tix_ctl_write_val | PCI_TI_CTL_BAR_EN;
pci_tix_ctl_write_val = pci_tix_ctl_write_val | PCI_TIx_CTL_RTT_VAL;
pci_tix_ctl_write_val = pci_tix_ctl_write_val | PCI_TIx_CTL_WTT_VAL;
pci_tix_ctl_write_val = pci_tix_ctl_write_val | PCI_TI_CTL_CI_;
temp = bs << 24;
pci_tix_ctl_write_val = pci_tix_ctl_write_val |
( temp & PCI_TI_CTL_BS);
pci_tix_ctl_write_val = pci_tix_ctl_write_val |
( rd_amt & PCI_TI_CTL_RD_AMT);
if ( bus == PCI1 )
{
pci_tix_baddr_ptr = &(pspan->p1_cfg.bst[img_num]);
pci_tix_taddr_ptr = &(pspan->p1.ti[img_num].taddr);
pci_tix_ctl_ptr = &(pspan->p1.ti[img_num].ctl);
}
else if ( bus == PCI2 )
{
pci_tix_baddr_ptr = &(pspan->p2_cfg.bst[img_num]);
pci_tix_taddr_ptr = &(pspan->p2.ti[img_num].taddr);
pci_tix_ctl_ptr = &(pspan->p2.ti[img_num].ctl);
}
else
{
retval = FAILURE;
}
*pci_tix_ctl_ptr = pci_tix_ctl_write_val;
/* only program base address register if baddr is not 0 */
if ( 0 != baddr )
*pci_tix_baddr_ptr = baddr;
/* only program translation address register if taddr is not 0 */
if ( 0 != taddr )
*pci_tix_taddr_ptr = taddr & PCI_TI_TADDR_TADDR;
temp = *pci_tix_ctl_ptr;
/* write failed - read back did not match */
if ( temp != pci_tix_ctl_write_val )
retval = FAILURE;
return( retval );
} /* PspanPciTargetImageSetup */
/*=========================================================================
* Function Name: PspanPbSlaveImageMiscSetup
*
* Arguments:
* pspan pointer to PowerSpan register space structure
* img_num image number (0-7)
* endian BIG_ENDIAN/LITTLE_ENDIAN/PPC_LITTLE_ENDIAN
* dest PCI1/PCI2
* prkeep TRUE/FALSE
*
* (refer to the PowerSpan Registers Spec for descriptions of the endian,
* dest and prkeep fields)
*
* Description:
* Sets the PB Slave Image Endian/Dest/PRKEEP bits.
*
* Return Value: SUCCESS/FAILURE
*
=========================================================================*/
UINT32 PspanPbSlaveImageMiscSetup
(
PPSPAN pspan,
UINT32 img_num,
UINT32 endian,
UINT32 dest,
UINT32 prkeep
)
{
UINT32 retval;
VUINT32 *pb_six_ctl_ptr;
UINT32 temp;
retval = SUCCESS;
pb_six_ctl_ptr = &(pspan->pb_si[0].ctl);
pb_six_ctl_ptr = pb_six_ctl_ptr + 4*img_num;
temp = *pb_six_ctl_ptr;
if ( endian == BIG_ENDIAN )
temp = temp | ( PB_SIx_CTL_BE_VAL & PB_SI_CTL_END);
else if ( endian == PPC_LITTLE_ENDIAN )
temp = temp | ( PB_SIx_CTL_PPC_LE_VAL & PB_SI_CTL_END );
else if ( endian == LITTLE_ENDIAN )
temp = temp | ( PB_SIx_CTL_LE_VAL & PB_SI_CTL_END);
if ( dest == PCI1 )
temp = temp & ~PB_SI_CTL_DEST;
else if ( dest == PCI2 )
temp = temp | PB_SI_CTL_DEST;
if ( prkeep == FALSE )
temp = temp & ~PB_SI_CTL_PRKEEP;
else if ( prkeep == TRUE )
temp = temp | PB_SI_CTL_PRKEEP;
*pb_six_ctl_ptr = temp;
return ( retval );
} /* PspanPbSlaveImageMiscSetup */
/*=========================================================================
* Function Name: PspanPciTargetImageMiscSetup
*
* Arguments:
* pspan pointer to PowerSpan register space structure
* bus PCI1/PCI2
* img_num image number (0-3)
* endian BIG_ENDIAN/LITTLE_ENDIAN/PPC_LITTLE_ENDIAN
* dest PB/PCI1/PCI2
* prkeep TRUE/FALSE
*
* (refer to the PowerSpan Registers Spec for descriptions of the endian,
* dest and prkeep fields)
*
* Description:
* Sets the PCI Target Endian/Dest/PRKEEP bits.
*
* Return Value: SUCCESS/FAILURE
*
=========================================================================*/
UINT32 PspanPciTargetImageMiscSetup
(
PPSPAN pspan,
UINT32 bus,
UINT32 img_num,
UINT32 endian,
UINT32 dest,
UINT32 prkeep
)
{
UINT32 retval;
VUINT32 *pci_tix_ctl_ptr;
UINT32 temp;
retval = SUCCESS;
if ( bus == PCI1 )
pci_tix_ctl_ptr = &(pspan->p1.ti[img_num].ctl);
else
pci_tix_ctl_ptr = &(pspan->p2.ti[img_num].ctl);
temp = *pci_tix_ctl_ptr;
if ( endian == BIG_ENDIAN )
temp = temp | ( PB_SIx_CTL_BE_VAL & PB_SI_CTL_END);
else if ( endian == PPC_LITTLE_ENDIAN )
temp = temp | ( PB_SIx_CTL_PPC_LE_VAL & PB_SI_CTL_END);
else if ( endian == LITTLE_ENDIAN )
temp = temp | ( PB_SIx_CTL_LE_VAL & PB_SI_CTL_END);
if ( dest == PB )
temp = temp & ~PCI_TI_CTL_DEST;
else if ( dest == PCI1 || dest == PCI2 )
temp = temp | PCI_TI_CTL_DEST;
if ( prkeep == FALSE )
temp = temp & ~PCI_TI_CTL_PRKEEP;
else if ( prkeep == TRUE )
temp = temp | PCI_TI_CTL_PRKEEP;
*pci_tix_ctl_ptr = temp;
return ( retval );
} /* PspanPciTargetImageMiscSetup */
/*=========================================================================
* Function Name: PspanImageControlDump
*
* Arguments:
* pspan pointer to PowerSpan register space structure
*
* Description:
* Reads all PowerSpan image registers.
*
* Return Value: SUCCESS/FAILURE
*
=========================================================================*/
UINT32 PspanImageControlDump
(
PPSPAN pspan
)
{
UINT32 retval;
VUINT32 ctl_read_val;
VUINT32 baddr_read_val;
VUINT32 taddr_read_val;
VUINT32 *ctl_ptr;
VUINT32 *baddr_ptr;
VUINT32 *taddr_ptr;
int count;
retval = SUCCESS;
DBG0( "\r\n" );
/* PCI 1 */
ctl_ptr = &(pspan->p1.ti[0].ctl);
baddr_ptr = &(pspan->p1_cfg.bst[0]);
taddr_ptr = &(pspan->p1.ti[0].taddr);
for ( count = 0; count < 4; count++ )
{
ctl_read_val = *ctl_ptr;
baddr_read_val = *baddr_ptr;
taddr_read_val = *taddr_ptr;
ctl_ptr = ctl_ptr + 4;
baddr_ptr = baddr_ptr + 1;
taddr_ptr = taddr_ptr + 4;
printf( "P1_TIx_CTL [%d]: %08x\r\n", count, ctl_read_val );
printf( "P1_BSTx [%d]: %08x\r\n", count, baddr_read_val );
printf( "P1_TIx_TADDR[%d]: %08x\r\n", count, taddr_read_val );
}
/* PCI 2 */
ctl_ptr = &(pspan->p2.ti[0].ctl);
baddr_ptr = &(pspan->p2_cfg.bst[0]);
taddr_ptr = &(pspan->p2.ti[0].taddr);
for ( count = 0; count < 4; count++ )
{
ctl_read_val = *ctl_ptr;
baddr_read_val = *baddr_ptr;
taddr_read_val = *taddr_ptr;
ctl_ptr = ctl_ptr + 4;
baddr_ptr = baddr_ptr + 1;
taddr_ptr = taddr_ptr + 4;
DBG2( "P2_TIx_CTL [%d]: %08x\r\n", count, ctl_read_val );
DBG2( "P2_BSTx [%d]: %08x\r\n", count, baddr_read_val );
DBG2( "P2_TIx_TADDR[%d]: %08x\r\n", count, taddr_read_val );
}
/* PB */
ctl_ptr = &(pspan->pb_si[0].ctl);
baddr_ptr = &(pspan->pb_si[0].baddr);
taddr_ptr = &(pspan->pb_si[0].taddr);
for ( count = 0; count < 8; count++ )
{
ctl_read_val = *ctl_ptr;
baddr_read_val = *baddr_ptr;
taddr_read_val = *taddr_ptr;
ctl_ptr = ctl_ptr + 4;
baddr_ptr = baddr_ptr + 4;
taddr_ptr = taddr_ptr + 4;
printf( "PB_SIx_CTL [%d]: %08x\r\n", count, ctl_read_val );
printf( "PB_SIx_BADDR[%d]: %08x\r\n", count, baddr_read_val );
printf( "PB_SIx_TADDR[%d]: %08x\r\n", count, taddr_read_val );
}
return ( retval );
} /* PspanImageControlDump */
/*=========================================================================
* Function Name: PspanImagesSetup
*
* Arguments:
* pspan pointer to PowerSpan register space structure
*
* Description:
* Setup all PowerSpan images.
*
* Return Value: SUCCESS/FAILURE
*
=========================================================================*/
UINT32 PspanImagesSetup
(
PPSPAN pspan
)
{
UINT32 retval;
retval = SUCCESS;
/* Enable PCI Master and Target for Memory Accesses */
PspanEnablePciMemAccess( pspan );
#ifdef MONITOR_TEST
/* Setup PCI 1 Target Images */
PspanPciTargetImageSetup( pspan,
PCI1, 0, PCI1_TI0_BASE_ADDR,
PCI1_TI0_XLAT_ADDR,
PCI1_TI0_BLOCK_SIZE,
PCI1_TI0_RD_AMT );
PspanPciTargetImageSetup( pspan,
PCI1, 1, PCI1_TI1_BASE_ADDR,
PCI1_TI1_XLAT_ADDR,
PCI1_TI1_BLOCK_SIZE,
PCI1_TI1_RD_AMT );
/* Setup PCI 2 Target Images */
PspanPciTargetImageSetup( pspan,
PCI2, 0, PCI2_TI0_BASE_ADDR,
PCI2_TI0_XLAT_ADDR,
PCI2_TI0_BLOCK_SIZE,
PCI2_TI0_RD_AMT );
PspanPciTargetImageSetup( pspan,
PCI2, 1, PCI2_TI1_BASE_ADDR,
PCI2_TI1_XLAT_ADDR,
PCI2_TI1_BLOCK_SIZE,
PCI2_TI1_RD_AMT );
PspanPciTargetImageSetup( pspan,
PCI2, 2, PCI2_TI2_BASE_ADDR,
PCI2_TI2_XLAT_ADDR,
PCI2_TI2_BLOCK_SIZE,
PCI2_TI2_RD_AMT );
PspanPciTargetImageSetup( pspan,
PCI2, 3, PCI2_TI3_BASE_ADDR,
PCI2_TI3_XLAT_ADDR,
PCI2_TI3_BLOCK_SIZE,
PCI2_TI3_RD_AMT );
/* PCI Target Images Misc Setup */
PspanPciTargetImageMiscSetup( pspan,
PCI1, 0,
LITTLE_ENDIAN,
PB, FALSE );
PspanPciTargetImageMiscSetup( pspan,
PCI1, 1,
LITTLE_ENDIAN,
PCI2, FALSE );
PspanPciTargetImageMiscSetup( pspan,
PCI2, 0,
LITTLE_ENDIAN,
PB, FALSE );
PspanPciTargetImageMiscSetup( pspan,
PCI2, 1,
LITTLE_ENDIAN,
PCI1, FALSE );
PspanPciTargetImageMiscSetup( pspan,
PCI2, 2,
LITTLE_ENDIAN,
PCI1, FALSE );
PspanPciTargetImageMiscSetup( pspan,
PCI2, 3,
LITTLE_ENDIAN,
PCI1, FALSE );
/* Setup PB Slave Images */
PspanPbSlaveImageSetup( pspan,
0, PB_SI0_BASE_ADDR,
PB_SI0_XLAT_ADDR,
PB_SI0_BLOCK_SIZE,
PB_SI0_RD_AMT );
PspanPbSlaveImageSetup( pspan,
1, PB_SI1_BASE_ADDR,
PB_SI1_XLAT_ADDR,
PB_SI1_BLOCK_SIZE,
PB_SI1_RD_AMT );
PspanPbSlaveImageSetup( pspan,
2, PB_SI2_BASE_ADDR,
PB_SI2_XLAT_ADDR,
PB_SI2_BLOCK_SIZE,
PB_SI2_RD_AMT );
PspanPbSlaveImageSetup( pspan,
3, PB_SI3_BASE_ADDR,
PB_SI3_XLAT_ADDR,
PB_SI3_BLOCK_SIZE,
PB_SI3_RD_AMT );
PspanPbSlaveImageSetup( pspan,
4, PB_SI4_BASE_ADDR,
PB_SI4_XLAT_ADDR,
PB_SI4_BLOCK_SIZE,
PB_SI4_RD_AMT );
PspanPbSlaveImageSetup( pspan,
5, PB_SI5_BASE_ADDR,
PB_SI5_XLAT_ADDR,
PB_SI5_BLOCK_SIZE,
PB_SI5_RD_AMT );
PspanPbSlaveImageSetup( pspan,
6, PB_SI6_BASE_ADDR,
PB_SI6_XLAT_ADDR,
PB_SI6_BLOCK_SIZE,
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