pspanlib.h

motorola 8260 CPU上面

/***************************************************************************
 $Id:$

 FILE    :   pspanLib.h
 Purpose :   Header file for Misc PowerSpan Register Routines
             (modified from pspanHWDVRoutines.h)
 Author  :   Wilson Li
 Date    :   2000.3.19

 Modification History:

 Date        Who   What

 3/19/00     WLI   Initial Implementation
 4/10/00     pjg   Tundra Powerspan Evaluation Board Initial Release 

 **************************************************************************/

#ifndef INCpspanLibh
#define INCpspanLibh

#include "pspan.h"

/*
 *  PowerSpan Images Memory Map (3/20/00)
 *  For Coppermine.
 *
 *  If the base/xlat address is 0, use the existing value
 *  given from host.
 *
 *  PB Memory Map
 *  -----------------------
 *  0x00000000    64 MB  SDRAM
 *
 *  0xa0000000    32 MB  PB Image 0 to P1 QSpan II 1
 *  0xa2000000    32 MB  PB Image 1 to P1 QSpan II 2
 *  0xa4000000    32 MB  PB Image 2 to P1 PSpan Image 0
 *  0xa6000000    32 MB  PB Image 3 to P1 PSpan Image 1
 *  0xa8000000    64 MB  PB Image 4 to P2 QSpan II + QSpan II Regs
 *
 *  0x04700000   128 KB  8260 Internal Memory Space
 *  0x04720000    32 KB  Coppermine BCSRs
 *  0x04728000     4 KB  PB Register Image
 *  0x04729000     4 KB  PB Image 5 to P1 QSpan II 1 Regs
 *  0x0472a000     4 KB  PB Image 6 to P1 QSpan II 2 Regs
 *  0x0472b000     4 KB  PB Image 7 to P1 PSpan Regs
 *
 *  0xfe000000   512 KB  Flash
 *
 *  Note:  The above requires 4 DBAT registers if the MMU is enabled.
 *   64 MB DBAT0:  SDRAM
 *  256 MB DBAT1:  PowerSpan PB Images 0-4
 *  256 KB DBAT2:  8260 Internal Space, Coppermine BCSRs, PowerSpan Regs,
 *                 PowerSpan PB Images 5-7
 *   32 MB DBAT3:  Flash
 *  
 *  P1 PowerSpan Memory Map
 *  -----------------------
 *  0xXXXXXXXX     4 KB  P1 Register Image (address assigned by host)
 *  0xXXXXXXXX    32 MB  P1 Image 0 to PB SDRAM (address assigned by host)
 *  0xXXXXXXXX    32 MB  P1 Image 1 to P1 QSpan II (address assigned by host)
 *
 *  P2 PowerSpan Memory Map
 *  -----------------------
 *  0x10000000    32 MB  P2 Image 0 to PB SDRAM
 *  0x20000000    32 MB  P2 Image 1 to P1 QSpan II 1
 *  0x30000000    32 MB  P2 Image 2 to P1 QSpan II 2
 *  0x40000000    32 MB  P2 Image 3 to P1 QSpan II 2
 *  0xf0000000    32 MB  QSpan II Image 0  (from PB image 4)
 *  0xf2000000     4 KB  QSpan II Regs  (from PB image 4)
 *
 *  The following PowerSpan address registers in the PowerSpan are not programmed by 
 *  PowerSpan_Images_Setup() on the Coppermine.  They values must be obtained
 *  by PCI config writes done by the host to PowerSpan config space and QSpan II
 *  config space.
 *
 *  P1_BSREG (leave the register as is)
 *  P1_BST0  (leave the register as is)
 *  P1_BST1  (leave the register as is)
 *
 *  P2_TI1_TADDR  QSpan II 1 on P1
 *  P2_TI2_TADDR  QSpan II 2 on P1
 *  P2_TI3_TADDR  PSpan on P1 (the other PSpan)
 *
 *  PB_SI0_TADDR  QSpan II 1 on P1
 *  PB_SI1_TADDR  QSpan II 2 on P1
 *  PB_SI2_TADDR  PSpan Image 0 on P1 (the other PSpan)
 *  PB_SI3_TADDR  PSpan Image 1 on P1 (the other PSpan)
 *  PB_SI5_TADDR  QSpan II 1 Regs on P1
 *  PB_SI6_TADDR  QSpan II 2 Regs on P1
 *  PB_SI7_TADDR  PSpan Regs on P1 (the other PSpan)
 *
 *
 *  The defines below until "Misc Defines" are defines for
 *  programming PowerSpan slave/target images used by
 *  the routine PspanImagesSetup().
 *
 */
#define PS_BASE_DEFAULT          0x30000000 /* from PB */

#define PCI1_TI0_BASE_ADDR       0x00000000 /* from host */
#define PCI1_TI1_BASE_ADDR       0x00000000 /* from host */
#define PCI1_TI2_BASE_ADDR       0x00000000 /* from host */
#define PCI1_TI3_BASE_ADDR       0x00000000 /* from host */

#define PCI1_TI0_XLAT_ADDR       0x02000000 /* 60x SDRAM */
#define PCI1_TI1_XLAT_ADDR       0xf0000000 /* to PCI 2 QSpan 2 */
#define PCI1_TI2_XLAT_ADDR       0x00000000 /* not used */
#define PCI1_TI3_XLAT_ADDR       0x00000000 /* not used */

#define PCI2_TI0_BASE_ADDR       0x10000000 /* P2 Image 0 */
#define PCI2_TI1_BASE_ADDR       0x20000000 /* P2 Image 1 */
#define PCI2_TI2_BASE_ADDR       0x30000000 /* P2 Image 2 */
#define PCI2_TI3_BASE_ADDR       0x40000000 /* P2 Image 3 */

/* 
 * The translation address from P1 needs to be obtained from 
 * host.
 */
#define PCI2_TI0_XLAT_ADDR       0x02000000 /* 60x SDRAM */
#define PCI2_TI1_XLAT_ADDR       0x00000000 /* from host */
#define PCI2_TI2_XLAT_ADDR       0x00000000 /* from host */
#define PCI2_TI3_XLAT_ADDR       0x00000000 /* from host */

#define PB_SI0_BASE_ADDR         0xa0000000 /* P1 QSpan II 1 Image 0 */
#define PB_SI1_BASE_ADDR         0xa2000000 /* P1 QSpan II 2 Image 0 */
#define PB_SI2_BASE_ADDR         0xa4000000 /* P1 PSpan Image 0 */
#define PB_SI3_BASE_ADDR         0xa6000000 /* P1 PSpan Image 1 */
#define PB_SI4_BASE_ADDR         0xa8000000 /* P2 QSpan II Image 0 + Regs */
#define PB_SI5_BASE_ADDR         0x04729000 /* P1 QSpan II 1 Regs */
#define PB_SI6_BASE_ADDR         0x0472a000 /* P1 QSpan II 2 Regs */
#define PB_SI7_BASE_ADDR         0x0472b000 /* P1 PSpan Regs */

#define PB_SI0_XLAT_ADDR         0x00000000 /* from host */
#define PB_SI1_XLAT_ADDR         0x00000000 /* from host */
#define PB_SI2_XLAT_ADDR         0x00000000 /* from host */
#define PB_SI3_XLAT_ADDR         0x00000000 /* from host */
#define PB_SI4_XLAT_ADDR         0xf0000000 /* P2 QSPan II Image 0 + Regs */
#define PB_SI5_XLAT_ADDR         0x00000000 /* from host */
#define PB_SI6_XLAT_ADDR         0x00000000 /* from host */
#define PB_SI7_XLAT_ADDR         0x00000000 /* from host */


/*
 *  PowerSpan Images Misc Defines
 *
 *  The block sizes are set for the Coppermine.
 *  All unused images have a value of 0.
 *
 */
#define PCI1_TI0_BLOCK_SIZE      0x00000009  /* 32 MB */
#define PCI1_TI1_BLOCK_SIZE      0x00000009  /* 32 MB */
#define PCI1_TI2_BLOCK_SIZE      0x00000000  /* not used */
#define PCI1_TI3_BLOCK_SIZE      0x00000000  /* not used */

#define PCI2_TI0_BLOCK_SIZE      0x00000009  /* 32 MB */
#define PCI2_TI1_BLOCK_SIZE      0x00000009  /* 32 MB */
#define PCI2_TI2_BLOCK_SIZE      0x00000009  /* 32 MB */
#define PCI2_TI3_BLOCK_SIZE      0x00000009  /* 32 MB */

#define PB_SI0_BLOCK_SIZE        0x0000000d  /* 32 MB */
#define PB_SI1_BLOCK_SIZE        0x0000000d  /* 32 MB */
#define PB_SI2_BLOCK_SIZE        0x0000000d  /* 32 MB */
#define PB_SI3_BLOCK_SIZE        0x0000000d  /* 32 MB */
#define PB_SI4_BLOCK_SIZE        0x0000000e  /* 64 MB */
#define PB_SI5_BLOCK_SIZE        0x00000000  /* 4  KB */
#define PB_SI6_BLOCK_SIZE        0x00000000  /* 4  KB */
#define PB_SI7_BLOCK_SIZE        0x00000000  /* 4  KB */


/*
 *  The default read amount is set to 32 Bytes for all the 
 *  images.
 *
 */
#define PCI1_TI0_RD_AMT          0x00000002
#define PCI1_TI1_RD_AMT          0x00000002
#define PCI1_TI2_RD_AMT          0x00000002
#define PCI1_TI3_RD_AMT          0x00000002

#define PCI2_TI0_RD_AMT          0x00000002
#define PCI2_TI1_RD_AMT          0x00000002
#define PCI2_TI2_RD_AMT          0x00000002
#define PCI2_TI3_RD_AMT          0x00000002

#define PB_SI0_RD_AMT            0x00000002
#define PB_SI1_RD_AMT            0x00000002
#define PB_SI2_RD_AMT            0x00000002
#define PB_SI3_RD_AMT            0x00000002
#define PB_SI4_RD_AMT            0x00000002
#define PB_SI5_RD_AMT            0x00000002
#define PB_SI6_RD_AMT            0x00000002
#define PB_SI7_RD_AMT            0x00000002

/* End of defines for PowerSpan_Images_Setup() */

/* Miscellaneous Definitions */

#define SUCCESS 0
#define FAILURE 1

#define FALSE   0
#define TRUE    1

#define READ    0
#define WRITE   1

#define PB                   0
#define PCI1                 1
#define PCI2                 2
#define BIG_ENDIAN           0
#define LITTLE_ENDIAN        1
#define PPC_LITTLE_ENDIAN    2

#define PS_PCI1_DEV_NUM      0
#define PS_PCI2_DEV_NUM      0

#define PCI_TIx_CTL_RTT_VAL           0x000a0000
#define PCI_TIx_CTL_WTT_VAL           0x00000200
#define PCI_TIx_CTL_LE_VAL            0x00000000
#define PCI_TIx_CTL_PPC_LE_VAL        0x00000020
#define PCI_TIx_CTL_BE_VAL            0x00000040
#define PB_SIx_CTL_LE_VAL             0x00000000
#define PB_SIx_CTL_PPC_LE_VAL         0x00000020
#define PB_SIx_CTL_BE_VAL             0x00000040
#define DMAx_TCR_SRC_PORT_P1_VAL      0x00000000
#define DMAx_TCR_SRC_PORT_P2_VAL      0x40000000
#define DMAx_TCR_SRC_PORT_PB_VAL      0x80000000
#define DMAx_TCR_DST_PORT_P1_VAL      0x00000000
#define DMAx_TCR_DST_PORT_P2_VAL      0x10000000
#define DMAx_TCR_DST_PORT_PB_VAL      0x20000000
#define DMAx_ATTR_CPA_PORT_P1_VAL     0x00000000
#define DMAx_ATTR_CPA_PORT_P2_VAL     0x40000000
#define DMAx_ATTR_CPA_PORT_PB_VAL     0x80000000
#define IMR_MAP_P1_INTA_VAL           0x00000000
#define IMR_MAP_P2_INTA_VAL           0x22222222
#define IMR_MAP_INT0_VAL              0x44444444
#define IMR_MAP_INT1_VAL              0x66666666
#define IMR_MAP_INT2_VAL              0x88888888
#define IMR_MAP_INT3_VAL              0xaaaaaaaa
#define IMR_MAP_INT4_VAL              0xcccccccc
#define IMR_MAP_INT5_VAL              0xeeeeeeee

/* Print Macros */

#ifdef DBG_MACROS
#define DBG0(a) printf(a);
#define DBG1(a,b) printf(a,b);
#define DBG2(a,b,c) printf(a,b,c);
#define DBG3(a,b,c,d) printf(a,b,c,d);
#define DBG4(a,b,c,d,e) printf(a,b,c,d,e);
#define DBG5(a,b,c,d,e,f) printf(a,b,c,d,e,f);
#define DBG6(a,b,c,d,e,f,g) printf(a,b,c,d,e,f,g);
#else
#define DBG0(a) 
#define DBG1(a,b) 
#define DBG2(a,b,c) 
#define DBG3(a,b,c,d) 
#define DBG4(a,b,c,d,e) 
#define DBG5(a,b,c,d,e,f) 
#define DBG6(a,b,c,d,e,f,g) 
#endif /* DBG_MACROS */

struct PowerSpanCmdPktDef {
        VUINT32 Reserved00;
        VUINT32 DMAx_SRC_ADDR;
        VUINT32 Reserved08;
        VUINT32 DMAx_DST_ADDR;
        VUINT32 Reserved10;
        VUINT32 DMAx_TCR;
        VUINT32 Reserved18;
        VUINT32 DMAx_CPP;
};

/* Function Prototypes */

UINT32 PspanInit(PPSPAN pspan);

UINT32 PspanPciConfigRead ( 
  PPSPAN pspan,
  UINT32 dest,
  UINT32 dev_num,
  UINT32 reg_offset 
  );                

UINT32 PspanPciConfigWrite (
   PPSPAN pspan,
   UINT32 dest,
   UINT32 dev_num,
   UINT32 reg_offset,
   UINT32 data 
   );

UINT32 PspanPciProbe (
  PPSPAN pspan, 
  UINT32 dest 
  );

UINT32 PspanPciFindDevice ( 
  PPSPAN pspan,
  UINT32 dest,
  UINT32 starting_dev_num,
  UINT32 dev_ven_id,
  UINT32 *dev_num 
  );
 
UINT32 PspanEnablePciMemAccess ( 
  PPSPAN pspan 
  );

UINT32 PspanPbSlaveImageSetup ( 
  PPSPAN pspan,
  UINT32 img_num,
  UINT32 baddr,
  UINT32 taddr,
  UINT32 bs,
  UINT32 rd_amt 
  );

UINT32 PspanPciTargetImageSetup ( 
  PPSPAN pspan,
  UINT32 bus,
  UINT32 img_num,
  UINT32 baddr,
  UINT32 taddr,
  UINT32 bs,
  UINT32 rd_amt 
  );

UINT32 PspanPbSlaveImageMiscSetup ( 
  PPSPAN pspan,
  UINT32 img_num,
  UINT32 endian,
  UINT32 dest,
  UINT32 prkeep 
  );

UINT32 PspanPciTargetImageMiscSetup ( 
  PPSPAN pspan,
  UINT32 bus,
  UINT32 img_num,
  UINT32 endian,
  UINT32 dest,
  UINT32 prkeep 
  );                      

UINT32 PspanImageControlDump ( 
  PPSPAN pspan
  );
    
UINT32 PspanImagesSetup ( 
  PPSPAN pspan
  );

void PspanExtendedCyles (
  PPSPAN pspan,
  UINT32 enable_disable
  );

UINT32 PspanInterruptsSetup (
  PPSPAN pspan 
  );
                                   
UINT32 PspanSimpleDirectModeDma ( 
  PPSPAN pspan,
  UINT32 src_addr,
  UINT32 dst_addr,
  UINT32 src_port,
  UINT32 dst_port,
  UINT32 byte_count 
  );

UINT32 PspanCreateCommandPacket ( 
  struct PowerSpanCmdPktDef *p_PowerSpanCmdPktDef,
  UINT32 src_addr,
  UINT32 dst_addr,
  UINT32 src_port,
  UINT32 dst_port,
  UINT32 byte_count,
  struct PowerSpanCmdPktDef *next_cmd_pkt_ptr,
  UINT32 last
  );

UINT32 PspanSimpleLinkedListModeDma (
  PPSPAN pspan,
  UINT32 src_addr,
  UINT32 dst_addr,
  UINT32 src_port,
  UINT32 dst_port,
  UINT32 byte_count
  );
 
UINT32 PspanLinkedListDma (
  PPSPAN pspan,
  struct PowerSpanCmdPktDef *cmd_ppkt,
  UINT32 src_addr0,
  UINT32 dst_addr0,
  UINT32 src_port0,
  UINT32 dst_port0,
  UINT32 byte_count0,
  UINT32 src_addr1,
  UINT32 dst_addr1,
  UINT32 src_port1,
  UINT32 dst_port1,
  UINT32 byte_count1,
  UINT32 src_addr2,
  UINT32 dst_addr2,
  UINT32 src_port2,
  UINT32 dst_port2,
  UINT32 byte_count2
  );

UINT32 PspanI2c(
  PPSPAN pspan,
  UINT32 addr,
  UINT32 data,
  UINT32 dev_code,
  UINT32 chip_select,
  UINT32 read_write_,
  UINT32 *result
  );

UINT32 PspanI2cWrite ( 
  PPSPAN pspan,
  UINT32 addr,
  UINT32 data,
  UINT32 chip_select
  );

UINT32 PspanI2cRead (
  PPSPAN pspan,
  UINT32 addr,
  UINT32 chip_select,
  UINT32 *result
  );                  

UINT32 PspanVpd (
  PPSPAN pspan,
  UINT32 chip_select,
  UINT32 vpda,
  UINT32 *vpdd,
  UINT32 read_write_
  );

UINT32 PspanRegsDump ( 
  PPSPAN pspan 
  );

UINT32 PspanDirectModeDma ( 
  PPSPAN pspan,
  UINT32 src_addr,
  UINT32 dst_addr,
  UINT32 src_port,
  UINT32 dst_port,
  UINT32 byte_count,
  UINT32 channel 
  );

UINT32 PspanIsDmaDone (
  PPSPAN pspan,
  UINT32 channel
  );

UINT32 PspanCheckDmaStatus ( 
  PPSPAN pspan,
  UINT32 channel 
  );

UINT32 PspanProgramI2cLoadBits ( 
  UINT32 def_mem 
  );

UINT32 PspanWriteI2cLoadTable ( 
  unsigned char* i2c_table 
  );                  

UINT32 Swap_Word(
  UINT32 word_in
  );

#endif /* INCpspanLibh*/