rominit.s

motorola 8260 CPU上面

	addis   r5,0,0xaa4a
	ori     r5,r5,0xa45A
        lis     r6, HIADJ (M8260_PSDMR (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_PSDMR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	addis   r0,0,0
 
	/* do a single write to an arbitrary location */

	addi    r5,0,0x00FF      /* Load 0x000000FF into r5 */
	stb     r5,0(r0)         /* Write 0xFF to address 0 - bits [24-31] */

	/* issue a "CBR Refresh" command to SDRAM */

	addis   r5,0,0x8a4a
	ori     r5,r5,0xa45A
	stw	r5, 0 (r6)
 
	/* Loop 8 times, writing 0xFF to address 0 */

	addi	r7,0,0x0008
	mtspr	9,r7             /* Load spr CTR with 8 */
	addi 	r8,0,0x00FF      /* Load 0x000000FF into r8 */
 
SdramWrLoop:
 
	stb  	r8,0(r0)        	/* Write 0xFF to address 0 */
	bc   	16,0,SdramWrLoop	/* Decrement CTR, and possibly branch */
 
	/* issue a "Mode Register Write" command to SDRAM */

	addis   r5,0,0x9a4a
	ori     r5,r5,0xa45A
	stw	r5, 0 (r6)
 
	/* do a single write to an arbitrary location */

	addi    r8,0,0x00FF      /* Load 0x000000FF into r8 */
	stb     r8,0x110(r0)         /* Write 0xFF to address 0 - bits [24-31] */

	/* enable refresh services and put SDRAM into normal operation */

	addis   r5,0,0xc24a
	ori     r5,r5,0xa45e
	stw	r5, 0 (r6)

	lis	r4, HIADJ (0x04710000)	
	addi	r4, r4, LO (0x04710000)

/* 8260pc */
#define INCLUDE_LOC_SDRAM

#ifdef INCLUDE_LOC_SDRAM
 
   addi     r5,0,0x0021      
   stb      r5,0x01a4(r4)      /* store byte - bits[24-31] */
 
   addis    r8,0,0x0200     /* R3 holds the value temporarily */
   ori      r8,r8,0x1861
 
   addis    r5,0,0xFF00     /* R5 holds the value temporarily */
   ori      r5,r5,0x30c0
 
   stw        r5,0x0124(r4)
   stw        r8,0x0120 (r4)
 
   addis    r8,0,0xaa66

/* 8260pc */
/*   ori      r8,r8,0xA522	*/
   ori      r8,r8,0xA552
   stw      r8,0x0194 (r4)
 
   addis    r2,0,0x0200
   addi     r8,0,0xFFFF
   stb      r8,0(r2)         /* Write 0xFF to address 0x02000000 */

   addis    r8,0,0x8a66
/* 8260pc */
/*   ori      r8,r8,0xA522	*/
   ori      r8,r8,0xA552
   stw      r8,0x0194 (r4)
 
   addis r6,0,0
   ori   r6,r6,8
   mtspr 9,r6           /* Load CTR with 8. */
 
   addi  r8,0,0xFFFF      /* Load 0xFs into r8 */
 
locSdramWrLoop: 
 
   stb   r8,0(r2)         /* Write 0 to address 0x02000000 */
 
   bc    16,0,locSdramWrLoop /* Decrement CTR, then branch if the decremented CTR */
                          /* is not equal to 0 */

   addis    r8,0,0x9a66
/* 8260pc */
/*   ori      r8,r8,0xA522	*/
   ori      r8,r8,0xA552
   stw      r8,0x0194 (r4)
 
   addi     r8,0,0xFFFF
   stb      r8,0(r2)         /* Write 0xFF to address 0x02000000 */
 
   addis    r8,0,0xc266
/* 8260pc */
/*   ori      r8,r8,0xA522	*/
   ori      r8,r8,0xA552
   stw      r8,0x0194 (r4)
 
#endif /* INCLUDE_LOC_SDRAM */

        /* Zero-out registers: SPRGs */
 
	addis    r0,0,0
	isync				/* synchronize */

        mtspr   272,r0
        mtspr   273,r0
        mtspr   274,r0
        mtspr   275,r0
	isync				/* synchronize */
 
        /* zero-out the Segment registers */
 
        mtsr    0,r0
        isync
        mtsr    1,r0
        isync
        mtsr    2,r0
        isync
        mtsr    3,r0
        isync
        mtsr    4,r0
        isync
        mtsr    5,r0
        isync
        mtsr    6,r0
        isync
        mtsr    7,r0
        isync
        mtsr    8,r0
        isync
        mtsr    9,r0
        isync
        mtsr    10,r0
        isync
        mtsr    11,r0
        isync
        mtsr    12,r0
        isync
        mtsr    13,r0
        isync
        mtsr    14,r0
        isync
        mtsr    15,r0
        isync
 
	/* invalidate DBATs: clear VP and VS bits */

	mtspr   536,r0   /* Data bat register 0 upper */
	isync
	mtspr   538,r0   /* Data bat register 1 upper */
	isync
	mtspr   540,r0   /* Data bat register 2 upper */
	isync
	mtspr   542,r0   /* Data bat register 3 upper */
	isync
	
	/* invalidate IBATs: clear VP and VS bits */

	mtspr   528,r0   /* Instruction bat register 0 upper */
	isync
	mtspr   530,r0   /* Instruction bat register 1 upper */
	isync
	mtspr   532,r0   /* Instruction bat register 2 upper */
	isync
	mtspr   534,r0   /* Instruction bat register 3 upper */
	isync

	/* invalidate TLBs: loop on all TLB entries using r7 as an index */

	addi     r0,0,0x0020
	mtspr    9,r0			/* Load CTR with 32 */
	addi     r7,0,0            	/* Use r7 as the tlb index */

tlb_write_loop:
 
	tlbie    r7                	/* invalidate the tlb entry */
	sync
	addi     r7,r7,0x1000          	/* increment the index */
	bc       16,0,tlb_write_loop   	/* Decrement CTR, then branch if the */
				       	/* decremented CTR is not equal to 0 */
#if 0
        /* Turn off data and instruction cache control bits */
 
        mfspr   r7, HID0
        isync
	sync				/* synchronize */
	andi.	r7,r7,0x3FFF   		/* Clear DCE and ICE bits */
	mtspr	HID0,r7
        isync
	sync				/* synchronize */

#endif

#if 0 
tlb_write_loop:
 
	tlbie    r7                	/* invalidate the tlb entry */
	sync
	addi     r7,r7,0x1000          	/* increment the index */
	bc       16,0,tlb_write_loop   	/* Decrement CTR, then branch if the */
				       	/* decremented CTR is not equal to 0 */

        /* Turn off data and instruction cache control bits */
 
        mfspr   r7, HID0
        isync
	sync				/* synchronize */
	andi.	r7,r7,0x3FFF   		/* Clear DCE and ICE bits */
	mtspr	HID0,r7
        isync
	sync				/* synchronize */

	/* invalidate the MPU's data/instruction caches */

	ori	r5, r5, _PPC_HID0_ICE | _PPC_HID0_DCE
		                 /* r5 has invalidate bits set */
	or	r4, r4, r5	 /* set bits */
	sync
	isync
	mtspr	HID0, r4	/* HID0 = r4 */
	andc	r4, r4, r5	/* clear bits */
	isync
	mtspr	HID0, r4
	isync

	/* turn the instruction cache on */ 



	ori	r4, r4, _PPC_HID0_ICE | _PPC_HID0_ICFI	/* set ICE & ICFI */
	rlwinm	r5, r4, 0, _PPC_HID0_BIT_ICFI + 1, _PPC_HID0_BIT_ICFI - 1
	isync

	/*
	 * The setting of the instruction cache enable (ICE) bit must be
	 * preceded by an isync instruction to prevent the cache from being
	 * enabled or disabled while an instruction access is in progress.
	 */

	mtspr	HID0, r4	/* Enable Instr Cache & Inval cache */
	sync
	mtspr	HID0, r5	/* using 2 consec instructions */
#endif


#if 0
	/* Get the board revision number but do nothing for now */

	lis	r6, HIADJ (BCSR2)	/* load r6 with the BCSR2 address */
	lwz	r5, LO(BCSR2)(r6)	/* load r5 with the BCSR2 value */

	lis	r6, HI(BCSR2_BREVN)
	and	r5, r5, r6		/* extract board revision number */
#endif


/* 8260PC: Turn on icache */

	/* turn off data and instruction cache */

	mfspr	r5, HID0
	isync
	rlwinm	r4, r5, 0, _PPC_HID0_BIT_DCE + 1, _PPC_HID0_BIT_ICE - 1
	sync
	isync
	mtspr	HID0, r4	/* HDI0 = r4 */
	isync

	/* invalidate the MPU's data/instruction caches */

	ori	r5, r5, _PPC_HID0_ICE | _PPC_HID0_DCE
		                 /* r5 has invalidate bits set */
	or	r4, r4, r5	 /* set bits */
	sync
	isync
	mtspr	HID0, r4	/* HID0 = r4 */
	andc	r4, r4, r5	/* clear bits */
	isync
	mtspr	HID0, r4
	isync

	/* turn the instruction cache on */ 

	ori	r4, r4, _PPC_HID0_ICE | _PPC_HID0_ICFI	/* set ICE & ICFI */
	rlwinm	r5, r4, 0, _PPC_HID0_BIT_ICFI + 1, _PPC_HID0_BIT_ICFI - 1
	isync

	/*
	 * The setting of the instruction cache enable (ICE) bit must be
	 * preceded by an isync instruction to prevent the cache from being
	 * enabled or disabled while an instruction access is in progress.
	 */

	mtspr	HID0, r4	/* Enable Instr Cache & Inval cache */
	sync
	mtspr	HID0, r5	/* using 2 consec instructions */

/* 8260PC: end of icache turn on */

        /* initialize the stack pointer */

	lis	sp, HIADJ(STACK_ADRS)
	addi	sp, sp, LO(STACK_ADRS)
	
	/* go to C entry point */

	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

        lis     r7, HIADJ(romInit)
        addi    r7, r7, LO(romInit)
 
        lis     r8, HIADJ(ROM_TEXT_ADRS)
        addi    r8, r8, LO(ROM_TEXT_ADRS)
 
        lis	r6, HIADJ(romStart)	
        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */

	sub	r6, r6, r7		/* routine - entry point */
	add	r6, r6, r8 		/* + ROM base */

	mtspr	LR, r6				/* save destination address*/
						/* into LR register */
	blr				/* jump to the C entry point */