rominit.s

motorola 8260 CPU上面

/* romInit.s - Motorola 8260 processor card ROM initialization module */

	.data
	.globl  copyright_wind_river
	.long   copyright_wind_river



/*
modification history
--------------------
Dec 15, 2000 created by sjzhu
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 8 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"	
#include "sysLib.h"
#include "drv/timer/m8260Clock.h"
#include "drv/mem/m8260Siu.h"
#include "drv/mem/m8260Memc.h"

	/* internals */

	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */

	/* externals */

	.extern romStart	/* system initialization routine */

	.text
 .fill   1,1,HRCW_BYTE_0    /* byte 0 (MSByte) of the configuration master's */
                     /* Hard Reset Configuration Word */
 
 .fill   7,1,0       /* Fill with 7 zeros */
 .fill   1,1,HRCW_BYTE_1
 .fill   7,1,0
 .fill   1,1,HRCW_BYTE_2
 .fill   7,1,0
 .fill   1,1,HRCW_BYTE_3    /* This is the LSByte */
 .fill   7,1,0       /* Fill with 7 zeroes               */ 
 .fill   1,1,0x24    	    /* PowerSpan Config Word            */
 .fill   223,1,0     /* Fill remaining bytes with zeroes */
	.align 2



/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
*
* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:       

	bl	cold		/* jump to the cold boot initialization */
	nop
	bl	start		/* jump to the warm boot initialization */


	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1999 Wind River Systems, Inc."
	.align 2

cold:

        li      r3, BOOT_COLD   /* set cold boot as start type */

	addis    r4,0,0x0F01    /* R4 holds the IMMR base address */
	addis    r5,0,0x0000    /* Clear out all mask bits */
	ori      r5,r5,0x0836	 
	stw      r5,0x0104(r4)  /* option register for bank 0 */
	isync			/* synchronize */

	/*
	 * initialize the IMMR register before any non-core registers
	 * modification. The default IMMR base address was 0x0F000000,
	 * as originally programmed in the Hard Reset Configuration Word.
	 */

	lis	r4, HIADJ (INTERNAL_MEM_MAP_ADDR)	
	addi	r4, r4, LO (INTERNAL_MEM_MAP_ADDR)
	addis   r8,0,0x0F01			/* IMMR was at 0x0f000000 */
	stw     r4,0x01a8 (r8)			/* IMMR now at 0x04700000 */
        isync

/* 8260PC: Old comment */
	/*
	 * When the PowerPC 8260 is powered on, the processor fetches the
	 * instructions located at the address 0x100. We need to jump
	 * from the address 0x100 to the Flash space.
	 */


/* 8260PC: 8260 HRCW[CIP] and HRCW[BMS] have already specified the Flash space.  After bootup
	   from CS0~, HRCW is obtained and it will jump to the Flash space automatically.  No
	   need to hardcode the return address for jumping to Flash space as 860 case.
*/

/* #if 0 */
        lis     r4, HIADJ(start)                /* load r4 with the address */
        addi    r4, r4, LO(start)               /* of start */

        lis     r5, HIADJ(romInit)              /* load r5 with the address */
        addi    r5, r5, LO(romInit)             /* of romInit() */

        lis     r6, HIADJ(ROM_TEXT_ADRS)        /* load r6 with the address */
        addi    r6, r6, LO(ROM_TEXT_ADRS)       /* of ROM_TEXT_ADRS */

        sub     r4, r4, r5                      /*  */
        add     r4, r4, r6

        mtspr   LR, r4                          /* save destination address*/
                                              /* into LR register */
        blr                                     /* jump to flash mem address */
/* #endif */

/*  8260PC: return to Cold */
/*          blr                                      return */ 
         
start:

	/* set the MSR register to a known state */

	xor	r0, r0, r0		/* clear register R0 */
	isync				/* synchronize */
	mtmsr 	r0			/* clear the MSR register */
	isync				/* synchronize */

	/* program the SCCR: normal operation */
	
	lis	r5, HIADJ (M8260_SCCR_DFBRG_16)
	addi	r5, r5, LO (M8260_SCCR_DFBRG_16)
	lis	r6, HIADJ (M8260_SCCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_SCCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* SYPCR - turn off the system protection stuff */

	addi	r5, r5, LO (M8260_SYPCR_SWTC | M8260_SYPCR_BMT \
			   | M8260_SYPCR_PBME | M8260_SYPCR_LBME)
	lis	r6, HIADJ (M8260_SYPCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_SYPCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* program the BCR */

	addis   r5,0,0x8844
	ori		r5,r5,0x4000
	lis	r6, HIADJ (M8260_BCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_BCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the PPC_ACR */

	addi    r5,0,0x0002
	lis	r6, HIADJ (M8260_PPC_ACR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_PPC_ACR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the PPC_ALRH */

	addis   r5,0,0x0126
	ori     r5,r5,0x7893
	lis	r6, HIADJ (M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_PPC_ALRH (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
     
	/* program the SIUMCR */

	addis   r5,0,0x0e20
	ori     r5,r5,0x0000
	lis	r6, HIADJ (M8260_SIUMCR (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_SIUMCR (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the TESCR1 */

	addis   r5,0,0x0000
	ori     r5,r5,0x4000
	lis	r6, HIADJ (M8260_TESCR1 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_TESCR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/* program the LTESCR1 */

	addis   r5,0,0x0000
	ori     r5,r5,0x4000
	lis	r6, HIADJ (M8260_LTESCR1 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_LTESCR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
 
	/*
	 * Map the bank 0 to the flash area - On the ADS board at reset time
	 * the bank 0 is already used to map the flash.
	 */

	/* load the base register */

        lis     r5, HIADJ ((ROM_BASE_ADRS & M8260_BR_BA_MSK) | \
			   M8260_BR_PS_16 | M8260_BR_V)
        addi    r5, r5, LO ((ROM_BASE_ADRS & M8260_BR_BA_MSK) | \
			   M8260_BR_PS_16 | M8260_BR_V)

	lis	r6, HIADJ (M8260_BR0 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_BR0 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* load the option register */

/* 8260pc OR0: TRLX =1, ETHR = 10 */
/*        lis     r5, HIADJ ((ROM_BASE_ADRS & M8260_OR_AM_MSK) | M8260_OR_EHTR_8 \
                            | M8260_OR_CSNT_EARLY | M8260_OR_SCY_3_CLK)
        addi    r5, r5, LO ((ROM_BASE_ADRS & M8260_OR_AM_MSK) | M8260_OR_EHTR_8 \
                            | M8260_OR_CSNT_EARLY | M8260_OR_SCY_3_CLK)
*/

        lis     r5, HIADJ ((ROM_BASE_ADRS & M8260_OR_AM_MSK) | M8260_OR_EHTR_4 | M8260_OR_TRLX \
                            | M8260_OR_CSNT_EARLY | M8260_OR_SCY_3_CLK)
        addi    r5, r5, LO ((ROM_BASE_ADRS & M8260_OR_AM_MSK) | M8260_OR_EHTR_4 | M8260_OR_TRLX \
                            | M8260_OR_CSNT_EARLY | M8260_OR_SCY_3_CLK)

	lis	r6, HIADJ (M8260_OR0 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_OR0 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* map the bank 1 to the Latch */
	
/* 8260pc OR1: CSNT = 1, ACS = 10, ETHR = 01*/
/*	lis	r5, HIADJ ((0xffff8000 & M8260_OR_AM_MSK) \
			  | M8260_OR_SCY_1_CLK)

	addi	r5, r5, LO ((0xffff8000 & M8260_OR_AM_MSK) \
			  | M8260_OR_SCY_1_CLK )
*/
	lis	r5, HIADJ ((0xffff8000 & M8260_OR_AM_MSK) \
			  | M8260_OR_CSNT_EARLY | M8260_OR_ACS_DIV4 \
			  | M8260_OR_SCY_1_CLK | M8260_OR_EHTR_1)

	addi	r5, r5, LO ((0xffff8000 & M8260_OR_AM_MSK) \
			  | M8260_OR_CSNT_EARLY | M8260_OR_ACS_DIV4 \
			  | M8260_OR_SCY_1_CLK | M8260_OR_EHTR_1)
			   			    
	lis	r6, HIADJ (M8260_OR1 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_OR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
	
	/* write the proper value to the base register */
/* 8260pc : 8bit latch*/
/*	lis	r5, HIADJ (LATCH | M8260_BR_PS_32 | M8260_BR_V)	
	addi	r5, r5, LO (LATCH | M8260_BR_PS_32 | M8260_BR_V)
*/
	lis	r5, HIADJ (LATCH | M8260_BR_PS_8 | M8260_BR_V)	
	addi	r5, r5, LO (LATCH | M8260_BR_PS_8 | M8260_BR_V)

	lis	r6, HIADJ (M8260_BR1 (INTERNAL_MEM_MAP_ADDR))	
	addi	r6, r6, LO (M8260_BR1 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)
	
SdramInit:

	/* program the MPTPR */

/* 8260pc: MPTPR = 1900 */
/*	addi    r5,0,0x4000 */
	addi    r5,0,0x1900
        lis     r6, HIADJ (M8260_MPTPR (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_MPTPR (INTERNAL_MEM_MAP_ADDR))
	sth     r5, 0x0 (r6)      /* store upper half-word */

	/* program the PSRT */

	addi    r5,0,0x0021      
        lis     r6, HIADJ (M8260_PSRT (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_PSRT (INTERNAL_MEM_MAP_ADDR))
	stb     r5, 0x0 (r6)      /* store byte - bits[24-31] */
 
	/* load OR2 */

/* 8260pc : OR2 = 0xFE002EC0 */

        lis     r5, HIADJ ((0xfe000000 & M8260_OR_AM_MSK) | \
			    0x00000e20 | M8260_OR_SDRAM_BPD_4 \
                            | M8260_OR_SDRAM_NUMR_12 | M8260_OR_SDRAM_PM_NORM)
        addi    r5, r5, LO ((0xff000000 & M8260_OR_AM_MSK) | \
			    0x00000e00 | M8260_OR_SDRAM_BPD_4 \
                            | M8260_OR_SDRAM_NUMR_12 | M8260_OR_SDRAM_PM_NORM)

        lis     r6, HIADJ (M8260_OR2 (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_OR2 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	/* load BR2 */

	lis	r5, HIADJ (LOCAL_MEM_LOCAL_ADRS | M8260_BR_PS_64 | \
			   M8260_BR_MS_SDRAM_60X | M8260_BR_V)	
	addi	r5, r5, LO (LOCAL_MEM_LOCAL_ADRS | M8260_BR_PS_64 | \
			   M8260_BR_MS_SDRAM_60X | M8260_BR_V)

        lis     r6, HIADJ (M8260_BR2 (INTERNAL_MEM_MAP_ADDR))
        addi    r6, r6, LO (M8260_BR2 (INTERNAL_MEM_MAP_ADDR))
	stw	r5, 0 (r6)

	
	/* 
	 * program the PSDMR as explained below: 
	 * PBI is set to zero, since page-based interleaving is not
	 * supported on early silicon revisions
	 * Refresh services are off for now
	 * OP selects the "Precharge all banks" command
	 * SDAM = b001
	 * BSMA selects A15-A17 as bank select lines 
	 * A9 is selected as control pin for SDA10 on SDRAM
	 * 7-clock refresh recovery time
	 * precharge-to-activate interval is 3-clock time
	 * activate-to-read/write interval is 2-clock time
	 * Burst lenght is 4
	 * last data out to precharge is 1 clock
	 * write recovery time is 1 clock
	 * no external address multiplexing
	 * normal timing for the control lines
	 * CAS latency is 2
	 */