m8260cpm.h

motorola 8260 CPU上面

#define M8260_FPSMR_ETH_RSH	0x00100000          /* receive short frame */
#define M8260_FPSMR_ETH_CAM	0x00000400          /* CAM address matching */
#define M8260_FPSMR_ETH_BRO	0x00000200          /* broadcast enable */
#define M8260_FPSMR_ETH_CRC_32	0x00000080          /* use 32-bit CCITT CRC */
#define M8260_FPSMR_ETH_CRC_MASK	0x000000c0          /* CRC mask field */

/* FCC Ethernet Event and Mask Register definitions */
 
#define M8260_FEM_ETH_RES      0xff00          /* reserved mask */
#define M8260_FEM_ETH_EVENT    0x00ff          /* event mask */
#define M8260_FEM_ETH_GRA      0x0080          /* graceful stop event */
#define M8260_FEM_ETH_RXC      0x0040          /* rx control frame event */
#define M8260_FEM_ETH_TXC      0x0020          /* tx control frame event */
#define M8260_FEM_ETH_TXE      0x0010          /* transmission error event */
#define M8260_FEM_ETH_RXF      0x0008          /* frame received event */
#define M8260_FEM_ETH_BSY      0x0004          /* busy condition */
#define M8260_FEM_ETH_TXB      0x0002          /* buffer transmitted event */
#define M8260_FEM_ETH_RXB      0x0001          /* buffer received event */
 
/* FCC Ethernet Receive Buffer Descriptor definitions */
 
#define M8260_FETH_RBD_E       0x8000          /* buffer is empty */
#define M8260_FETH_RBD_W       0x2000          /* last BD in ring */
#define M8260_FETH_RBD_I       0x1000          /* interrupt on receive */
#define M8260_FETH_RBD_L       0x0800          /* buffer is last in frame */
#define M8260_FETH_RBD_F       0x0400          /* buffer is first in frame */
#define M8260_FETH_RBD_M       0x0100          /* miss bit for prom mode */
#define M8260_FETH_RBD_BC      0x0080          /* broadcast address frame */
#define M8260_FETH_RBD_MC      0x0040          /* multicast address frame */
#define M8260_FETH_RBD_LG      0x0020          /* frame length violation */
#define M8260_FETH_RBD_NO      0x0010          /* nonoctet aligned frame */
#define M8260_FETH_RBD_SH      0x0008          /* short frame received */
#define M8260_FETH_RBD_CR      0x0004          /* Rx CRC error */
#define M8260_FETH_RBD_OV      0x0002          /* overrun condition */
#define M8260_FETH_RBD_CL      0x0001          /* collision condition */
 
/* FCC Ethernet Transmit Buffer Descriptor definitions */
 
#define M8260_FETH_TBD_R       0x8000          /* buffer is ready */
#define M8260_FETH_TBD_PAD     0x4000          /* auto pad short frames */
#define M8260_FETH_TBD_W       0x2000          /* last BD in ring */
#define M8260_FETH_TBD_I       0x1000          /* interrupt on transmit */
#define M8260_FETH_TBD_L       0x0800          /* buffer is last in frame */
#define M8260_FETH_TBD_TC      0x0400          /* auto transmit CRC */
#define M8260_FETH_TBD_DEF     0x0200          /* defer indication */
#define M8260_FETH_TBD_HB      0x0100          /* heartbeat */
#define M8260_FETH_TBD_LC      0x0080          /* late collision */
#define M8260_FETH_TBD_RL      0x0040          /* retransmission limit */
#define M8260_FETH_TBD_RC      0x003c          /* retry count */
#define M8260_FETH_TBD_UN      0x0002          /* underrun */
#define M8260_FETH_TBD_CSL     0x0001          /* carrier sense lost */
 
/* Command Register definitions (CPCR - 0x119C0) */    
 
#define M8260_CPCR(base)   (CAST(VUINT32 *)((base) + 0x119C0)) /* CPCR */
#define M8260_CPCR_LATENCY (65536 * 400)	/* worst case exec latency */

#define	M8260_CPCR_RESET	0x80000000	/* software reset command */
#define M8260_CPCR_PAGE_MSK	0x7c000000	/* RAM page number */
#define M8260_CPCR_SBC_MSK     	0x03e00000	/* sub-block code */
#define M8260_CPCR_RES1     	0x001e0000	/* reserved */
#define M8260_CPCR_FLG		0x00010000	/* flag - command executing */ 
#define M8260_CPCR_RES2     	0x0000c000	/* reserved */
#define M8260_CPCR_MCN_MSK     	0x00003fc0	/* MCC channel number */
#define M8260_CPCR_RES3     	0x00000030	/* reserved */
#define M8260_CPCR_OP_MSK     	0x0000000f	/* command opcode */
#define M8260_CPCR_PAGE_SHIFT   0x1a		/* get to the page field */
#define M8260_CPCR_SBC_SHIFT   	0x15		/* get to the SBC field */
#define M8260_CPCR_MCN_SHIFT   	0x6		/* get to the MCC field */
#define M8260_CPCR_OP_SHIFT 	0x0		/* get to the opcode field */
#define M8260_CPCR_MCN_HDLC   	0x0		/* protocol code: HDLC */
#define M8260_CPCR_MCN_ATM   	0xa		/* protocol code: ATM */
#define M8260_CPCR_MCN_ETH   	0xc		/* protocol code: ETH */
#define M8260_CPCR_MCN_TRANS   	0xf		/* protocol code: TRANS */

#define	M8260_CPCR_OP(x)						\
    (((x) << M8260_CPCR_OP_SHIFT) & M8260_CPCR_OP_MSK)
    
#define	M8260_CPCR_SBC(x)						\
    (((x) << M8260_CPCR_SBC_SHIFT) & M8260_CPCR_SBC_MSK)

#define	M8260_CPCR_PAGE(x)						\
    (((x) << M8260_CPCR_PAGE_SHIFT) & M8260_CPCR_PAGE_MSK)

#define	M8260_CPCR_MCN(x)						\
    (((x) << M8260_CPCR_MCN_SHIFT) & M8260_CPCR_MCN_MSK)

/* CPCR - Sub-block code */

#define M8260_CPCR_SBC_FCC1     0x10			/* FCC1 channel */ 
#define M8260_CPCR_SBC_ATM_FCC1 0x0e			/* ATM on FCC1 */ 
#define M8260_CPCR_SBC_FCC2     0x11			/* FCC2 channel */ 
#define M8260_CPCR_SBC_ATM_FCC2 0x0e			/* ATM on FCC2 */ 
#define M8260_CPCR_SBC_FCC3     0x12			/* FCC3 channel */ 
#define M8260_CPCR_SBC_SCC1     0x04			/* SCC1 channel */ 
#define M8260_CPCR_SBC_SCC2     0x05			/* SCC2 channel */ 
#define M8260_CPCR_SBC_SCC3     0x06			/* SCC3 channel */ 
#define M8260_CPCR_SBC_SCC4     0x07			/* SCC4 channel */ 
#define M8260_CPCR_SBC_SMC1     0x08			/* SMC1 channel */ 
#define M8260_CPCR_SBC_SMC2     0x09			/* SMC2 channel */ 
#define M8260_CPCR_SBC_RAND     0x0e			/* RAND channel */ 
#define M8260_CPCR_SBC_SPI     	0x0a			/* SPI */ 
#define M8260_CPCR_SBC_I2C     	0x0b			/* I2C */ 
#define M8260_CPCR_SBC_TIMER    0x0f			/* TIMER */ 
#define M8260_CPCR_SBC_MCC1     0x1c			/* MCC1 channel */ 
#define M8260_CPCR_SBC_MCC2     0x1d			/* MCC2 channel */ 
#define M8260_CPCR_SBC_IDMA1    0x14			/* IDMA1 channel */ 
#define M8260_CPCR_SBC_IDMA2    0x15			/* IDMA2 channel */ 
#define M8260_CPCR_SBC_IDMA3    0x16			/* IDMA3 channel */ 
#define M8260_CPCR_SBC_IDMA4    0x17			/* IDMA4 channel */ 

/* CPCR - Page code */

#define M8260_CPCR_PAGE_FCC1    0x04			/* FCC1 channel */ 
#define M8260_CPCR_PAGE_FCC2    0x05			/* FCC2 channel */ 
#define M8260_CPCR_PAGE_FCC3    0x06			/* FCC3 channel */ 
#define M8260_CPCR_PAGE_SCC1    0x00			/* SCC1 channel */ 
#define M8260_CPCR_PAGE_SCC2    0x01			/* SCC2 channel */ 
#define M8260_CPCR_PAGE_SCC3    0x02			/* SCC3 channel */ 
#define M8260_CPCR_PAGE_SCC4    0x03			/* SCC4 channel */ 
#define M8260_CPCR_PAGE_SMC1    0x07			/* SMC1 channel */ 
#define M8260_CPCR_PAGE_SMC2    0x08			/* SMC2 channel */ 
#define M8260_CPCR_PAGE_RAND    0x0a			/* RAND channel */ 
#define M8260_CPCR_PAGE_SPI     0x09			/* SPI */ 
#define M8260_CPCR_PAGE_I2C     0x0a			/* I2C */ 
#define M8260_CPCR_PAGE_TIMER   0x0a			/* TIMER */ 
#define M8260_CPCR_PAGE_MCC1    0x07			/* MCC1 channel */ 
#define M8260_CPCR_PAGE_MCC2    0x08			/* MCC2 channel */ 
#define M8260_CPCR_PAGE_IDMA1   0x07			/* IDMA1 channel */ 
#define M8260_CPCR_PAGE_IDMA2   0x08			/* IDMA2 channel */ 
#define M8260_CPCR_PAGE_IDMA3   0x09			/* IDMA3 channel */ 
#define M8260_CPCR_PAGE_IDMA4   0x0a			/* IDMA4 channel */ 

/* CPCR - opcodes */
 
#define M8260_CPCR_RT_INIT	0x0		/* Init rx and tx */
#define M8260_CPCR_RX_INIT   	0x1		/* init rx only */
#define M8260_CPCR_TX_INIT   	0x2		/* init tx only */
#define M8260_CPCR_HUNT      	0x3		/* rx frame hunt mode */
#define M8260_CPCR_TX_STOP      0x4		/* stop tx */
#define M8260_CPCR_TX_GRSTOP   	0x5		/* gracefully stop tx */
#define M8260_CPCR_TX_RESTART   0x6		/* restart tx */
#define M8260_CPCR_RX_CLOSE     0x7		/* close rx buffer */
#define M8260_CPCR_SET_GROUP 	0x8		/* set group address */
#define	M8260_CPCR_SET_TMR	0x8		/* set timer */
#define	M8260_CPCR_GCI_TMO	0x9		/* gci timeout */
#define	M8260_CPCR_IDMA_START	0x9		/* start idma */
#define	M8260_CPCR_MCC_RX_STOP	0x9		/* stop rx on MCC */
#define	M8260_CPCR_ATM_TX	0xa		/* ATM transmit */
#define M8260_CPCR_BCS_RESET 	0xa		/* blk chk seq reset */
#define	M8260_CPCR_GCI_ABRT	0xa		/* gci abort request */
#define	M8260_CPCR_IDMA_STOP	0xb		/* stop idma */
#define	M8260_CPCR_RANDOM	0xc		/* random number */

/* CMX FCC Clock Route Register bit definition (CMXFCR - 0x11B04) */

#define M8260_CMXFCR_GR1	0x80000000	/* Grant Support of FCC1 */
#define M8260_CMXFCR_FC1_MUX	0x40000000	/* FCC1 Connection - mux SI */
#define M8260_CMXFCR_R1CS_MSK	0x38000000	/* FCC1 Receive Clock Source */
#define M8260_CMXFCR_R1CS_BRG5	0x00000000	/* BRG5 clock source */
#define M8260_CMXFCR_R1CS_BRG6	0x08000000	/* BRG6 clock source */
#define M8260_CMXFCR_R1CS_BRG7	0x10000000	/* BRG7 clock source */
#define M8260_CMXFCR_R1CS_BRG8	0x18000000	/* BRG8 clock source */
#define M8260_CMXFCR_R1CS_CLK9	0x20000000	/* CLK9 clock source */
#define M8260_CMXFCR_R1CS_CLK10	0x28000000	/* CLK10 clock source */
#define M8260_CMXFCR_R1CS_CLK11	0x30000000	/* CLK11 clock source */
#define M8260_CMXFCR_R1CS_CLK12	0x38000000	/* CLK12 clock source */
#define M8260_CMXFCR_T1CS_MSK	0x07000000	/* FCC1 Transmit Clock Source */
#define M8260_CMXFCR_T1CS_BRG5	0x00000000	/* BRG5 clock source */
#define M8260_CMXFCR_T1CS_BRG6	0x01000000	/* BRG6 clock source */
#define M8260_CMXFCR_T1CS_BRG7	0x02000000	/* BRG7 clock source */
#define M8260_CMXFCR_T1CS_BRG8	0x03000000	/* BRG8 clock source */
#define M8260_CMXFCR_T1CS_CLK9	0x04000000	/* CLK9 clock source */
#define M8260_CMXFCR_T1CS_CLK10	0x05000000	/* CLK10 clock source */
#define M8260_CMXFCR_T1CS_CLK11	0x06000000	/* CLK11 clock source */
#define M8260_CMXFCR_T1CS_CLK12	0x07000000	/* CLK12 clock source */

#define M8260_CMXFCR_GR2	0x00800000	/* Grant Support of FCC2 */
#define M8260_CMXFCR_FC2_MUX	0x00400000	/* FCC2 Connection - mux SI */
#define M8260_CMXFCR_R2CS_MSK	0x00380000	/* FCC2 Receive Clock Source */
#define M8260_CMXFCR_R2CS_BRG5	0x00000000	/* BRG5 clock source */
#define M8260_CMXFCR_R2CS_BRG6	0x00080000	/* BRG6 clock source */
#define M8260_CMXFCR_R2CS_BRG7	0x00100000	/* BRG7 clock source */
#define M8260_CMXFCR_R2CS_BRG8	0x00180000	/* BRG8 clock source */
#define M8260_CMXFCR_R2CS_CLK13	0x00200000	/* CLK13 clock source */
#define M8260_CMXFCR_R2CS_CLK14	0x00280000	/* CLK14 clock source */
#define M8260_CMXFCR_R2CS_CLK15	0x00300000	/* CLK15 clock source */
#define M8260_CMXFCR_R2CS_CLK16	0x00380000	/* CLK16 clock source */
#define M8260_CMXFCR_T2CS_MSK	0x00070000	/* FCC2 Transmit Clock Source */
#define M8260_CMXFCR_T2CS_BRG5	0x00000000	/* BRG5 clock source */
#define M8260_CMXFCR_T2CS_BRG6	0x00010000	/* BRG6 clock source */
#define M8260_CMXFCR_T2CS_BRG7	0x00020000	/* BRG7 clock source */
#define M8260_CMXFCR_T2CS_BRG8	0x00030000	/* BRG8 clock source */
#define M8260_CMXFCR_T2CS_CLK13	0x00040000	/* CLK13 clock source */
#define M8260_CMXFCR_T2CS_CLK14	0x00050000	/* CLK14 clock source */
#define M8260_CMXFCR_T2CS_CLK15	0x00060000	/* CLK15 clock source */
#define M8260_CMXFCR_T2CS_CLK16	0x00070000	/* CLK16 clock source */

#define M8260_CMXFCR_GR3	0x00008000	/* Grant Support of FCC3 */
#define M8260_CMXFCR_FC3_MUX	0x00004000	/* FCC3 Connection - mux SI */
#define M8260_CMXFCR_R3CS_MSK	0x00003800	/* FCC3 Receive Clock Source */
#define M8260_CMXFCR_R3CS_BRG5	0x00000000	/* BRG5 clock source */
#define M8260_CMXFCR_R3CS_BRG6	0x00000800	/* BRG6 clock source */
#define M8260_CMXFCR_R3CS_BRG7	0x00001000	/* BRG7 clock source */
#define M8260_CMXFCR_R3CS_BRG8	0x00001800	/* BRG8 clock source */
#define M8260_CMXFCR_R3CS_CLK13	0x00002000	/* CLK13 clock source */
#define M8260_CMXFCR_R3CS_CLK14	0x00002800	/* CLK14 clock source */
#define M8260_CMXFCR_R3CS_CLK15	0x00003000	/* CLK15 clock source */
#define M8260_CMXFCR_R3CS_CLK16	0x00003800	/* CLK16 clock source */
#define M8260_CMXFCR_T3CS_MSK	0x00000700	/* FCC3 Transmit Clock Source */
#define M8260_CMXFCR_T3CS_BRG5	0x00000000	/* BRG5 clock source */
#define M8260_CMXFCR_T3CS_BRG6	0x00000100	/* BRG6 clock source */
#define M8260_CMXFCR_T3CS_BRG7	0x00000200	/* BRG7 clock source */
#define M8260_CMXFCR_T3CS_BRG8	0x00000300	/* BRG8 clock source */
#define M8260_CMXFCR_T3CS_CLK13	0x00000400	/* CLK13 clock source */
#define M8260_CMXFCR_T3CS_CLK14	0x00000500	/* CLK14 clock source */
#define M8260_CMXFCR_T3CS_CLK15	0x00000600	/* CLK15 clock source */
#define M8260_CMXFCR_T3CS_CLK16	0x00000700	/* CLK16 clock source */

/* CMX SCC Clock Route Register bit definition (CMXSCR - 0x11B08) */

#define M8260_CMXSCR_GR1	0x80000000	/* Grant Support of SCC1 */
#define M8260_CMXSCR_SC1_MUX	0x40000000	/* SCC1 Connection - mux SI */
#define M8260_CMXSCR_R1CS_MSK	0x38000000	/* SCC1 Receive Clock Source */
#define M8260_CMXSCR_R1CS_BRG1	0x00000000	/* BRG1 clock source */
#define M8260_CMXSCR_R1CS_BRG2	0x08000000	/* BRG2 clock source */
#define M8260_CMXSCR_R1CS_BRG3	0x10000000	/* BRG3 clock source */
#define M8260_CMXSCR_R1CS_BRG4	0x18000000	/* BRG4 clock source */
#define M8260_CMXSCR_R1CS_CLK11	0x20000000	/* CLK11 clock source */
#define M8260_CMXSCR_R1CS_CLK12	0x28000000	/* CLK12 clock source */
#define M8260_CMXSCR_R1CS_CLK3	0x30000000	/* CLK3 clock source */
#define M8260_CMXSCR_R1CS_CLK4	0x38000000	/* CLK4 clock source */
#define M8260_CMXSCR_T1CS_MSK	0x07000000	/* SCC1 Transmit Clock Source */
#define M8260_CMXSCR_T1CS_BRG1	0x00000000	/* BRG1 clock source */
#define M8260_CMXSCR_T1CS_BRG2	0x01000000	/* BRG2 clock source */
#define M8260_CMXSCR_T1CS_BRG3	0x02000000	/* BRG3 clock source */
#define M8260_CMXSCR_T1CS_BRG4	0x03000000	/* BRG4 clock source */
#define M8260_CMXSCR_T1CS_CLK11	0x04000000	/* CLK11 clock source */
#define M8260_CMXSCR_T1CS_CLK12	0x05000000	/* CLK12 clock source */
#define M8260_CMXSCR_T1CS_CLK3	0x06000000	/* CLK3 clock source */
#define M8260_CMXSCR_T1CS_CLK4	0x07000000	/* CLK4 clock source */

#define M8260_CMXSCR_GR2	0x00800000	/* Grant Support of SCC2 */
#define M8260_CMXSCR_SC2_MUX	0x00400000	/* SCC2 Connection - mux SI */
#define M8260_CMXSCR_R2CS_MSK	0x00380000	/* SCC2 Receive Clock Source */
#define M8260_CMXSCR_R2CS_BRG1	0x00000000	/* BRG1 clock source */
#define M8260_CMXSCR_R2CS_BRG2	0x00080000	/* BRG2 clock source */
#define M8260_CMXSCR_R2CS_BRG3	0x00100000	/* BRG3 clock source */
#define M8260_CMXSCR_R2CS_BRG4	0x00180000	/* BRG4 clock source */
#define M8260_CMXSCR_R2CS_CLK11	0x00200000	/* CLK11 clock source */
#define M8260_CMXSCR_R2CS_CLK12	0x00280000	/* CLK12 clock source */
#define M8260_CMXSCR_R2CS_CLK3	0x00300000	/* CLK3 clock source */
#define M8260_CMXSCR_R2CS_CLK4	0x00380000	/* CLK4 clock source */
#define M8260_CMXSCR_T2CS_MSK	0x00070000	/* SCC2 Transmit Clock Source */
#define M8260_CMXSCR_T2CS_BRG1	0x00000000	/* BRG1 clock source */
#define M8260_CMXSCR_T2CS_BRG2	0x00010000	/* BRG2 clock source */
#define M8260_CMXSCR_T2CS_BRG3	0x00020000	/* BRG3 clock source */
#define M8260_CMXSCR_T2CS_BRG4	0x00030000	/* BRG4 clock source */
#define M8260_CMXSCR_T2CS_CLK11	0x00040000	/* CLK11 clock source */
#define M8260_CMXSCR_T2CS_CLK12	0x00050000	/* CLK12 clock source */
#define M8260_CMXSCR_T2CS_CLK3	0x00060000	/* CLK3 clock source */
#define M8260_CMXSCR_T2CS_CLK4	0x00070000	/* CLK4 clock source */

#define M8260_CMXSCR_GR3	0x00008000	/* Grant Support of SCC3 */
#define M8260_CMXSCR_SC3_MUX	0x00004000	/* SCC3 Connection - mux SI */
#define M8260_CMXSCR_R3CS_MSK	0x00003800	/* SCC3 Receive Clock Source */
#define M8260_CMXSCR_R3CS_BRG1	0x00000000	/* BRG1 clock source */
#define M8260_CMXSCR_R3CS_BRG2	0x00000800	/* BRG2 clock source */
#define M8260_CMXSCR_R3CS_BRG3	0x00001000	/* BRG3 clock source */
#define M8260_CMXSCR_R3CS_BRG4	0x00001800	/* BRG4 clock source */
#define M8260_CMXSCR_R3CS_CLK5	0x00002000	/* CLK5 clock source */
#define M8260_CMXSCR_R3CS_CLK6	0x00002800	/* CLK6 clock source */
#define M8260_CMXSCR_R3CS_CLK7	0x00003000	/* CLK7 clock source */
#define M8260_CMXSCR_R3CS_CLK8	0x00003800	/* CLK8 clock source */
#define M8260_CMXSCR_T3CS_MSK	0x00000700	/* SCC3 Transmit Clock Source */