📄 smc_dtc_code0_fsm.hex
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; *****************************************************************
; * NOTICE: The information contained in this file is proprietary *
; * to SGS-THOMSON Microelectronics and is being made available *
; * to ST customers under strict non-disclosure agreements. *
; * Use or disclosure of this information is permissible only *
; * under the terms of the existing non-disclosure agreement. *
; *****************************************************************
; Written by Christophe BRICOUT
; Created by MPmanCompiler.exe (v3.0) Fri Jul 25 14:15:30 2003
;===================================================================
;
; SMART MEDIA CARD
;
;===================================================================
;--------------
; INIT SMC MODE
;--------------
; :init_smc_play_mode
;------------------
0xa0, ; 0 LD MSB 0
0xbf, ; 1 LD LSB 15
0x91, ; 2 LD DDR_PARALLEL
0x92, ; 3 LD OR_PARALLEL
0xba, ; 4 LD LSB 10
0x90, ; 5 LD DR_PARALLEL
0xb6, ; 6 LD LSB 6
0x98, ; 7 LD DDR_MPEG
0x99, ; 8 LD OR_MPEG
0x0, ; 9 NOP
0xb0, ; a LD LSB 0
0x97, ; b LD DR_MPEG
0xb9, ; c LD LSB 9 ; DATA_FLASH Port driven by FCI
0xa0, ; d LD MSB 0 ; data_flash port = intput
0x8d, ; e LD CTRL_FCI ; PARALLEL Port driven by FCI
0xb1, ; f LD LSB 1
0xa0, ; 10 LD MSB 0
0x81, ; 11 LD X ; X<=1
0x83, ; 12 LD MASK ; MASK = 1 ( used for XOR fct )
0x5, ; 13 STATUS STOP ; end of INIT
;---------------------
; SMC_DTC_Dummy_Write
;---------------------
0xa0, ; 14 LD MSB 0
0xb9, ; 15 LD LSB 9 ; DATA_FLASH Port driven by FCI
0x8d, ; 16 LD CTRL_FCI ; PARALLEL Port driven by FCI
0xb0, ; 17 LD LSB 0
0x85, ; 18 LD ADR_BUFFER01
0xbe, ; 19 LD LSB 14
0xaf, ; 1a LD MSB 15
0x84, ; 1b LD ADR_BUFFER00
0xdb, ; 1c LD A DATA_BUFFER0
0x88, ; 1d LD CMP00 ; load the even/odd bit
0xbf, ; 1e LD LSB 15
0xaf, ; 1f LD MSB 15
0x83, ; 20 LD MASK
0x84, ; 21 LD ADR_BUFFER00
0xdb, ; 22 LD A DATA_BUFFER0
0x82, ; 23 LD Y ; load number of pages
0x3c, ; 24 DECY
; :dummy_write
;-----------
0xc8, ; 25 LD A CMP00
0x31, ; 26 XOR
0x88, ; 27 LD CMP00 ; change the parity bit
0x28, ; 28 BCLR1
; JP :wait_buffer1_full
0x49, ; 29 JP 9
; :wait_buffer0_full
0xdf, ; 2a LD A BUFFER_MNGT
0x2a, ; 2b BCLR3
; JP :wait_buffer0_full
0x62, ; 2c JP -2
; :release_buffer0
;---------------
0xdf, ; 2d LD A BUFFER_MNGT
0x38, ; 2e BSET1
0x9f, ; 2f LD BUFFER_MNGT
0xb, ; 30 CP ALWAYS
; JP :update_buffer_flag
0x47, ; 31 JP 7
; :wait_buffer1_full
0xdf, ; 32 LD A BUFFER_MNGT
0x2b, ; 33 BCLR4
; JP :wait_buffer1_full
0x62, ; 34 JP -2
; :release_buffer1
;---------------
0xdf, ; 35 LD A BUFFER_MNGT
0x39, ; 36 BSET2
0x9f, ; 37 LD BUFFER_MNGT
; :update_buffer_flag
;------------------
0xb0, ; 38 LD LSB 0 ; clear the buffer full flags
0x9f, ; 39 LD BUFFER_MNGT
0xc2, ; 3a LD A Y
0x9b, ; 3b LD DATA_BUFFER0
0x3c, ; 3c DECY
; JP :dummy_write
0x78, ; 3d JP -24
0x5, ; 3e STATUS STOP
;---------------------------------
;For Bad Cluster recognition
;---------------------------------
0xa0, ; 3f LD MSB 0
0xbf, ; 40 LD LSB 15
0x91, ; 41 LD DDR_PARALLEL
0x92, ; 42 LD OR_PARALLEL
0xaf, ; 43 LD MSB 15
0x83, ; 44 LD MASK
0x31, ; 45 XOR
0x9f, ; 46 LD BUFFER_MNGT ; Clear segment offset
0x85, ; 47 LD ADR_BUFFER01
0x86, ; 48 LD ADR_BUFFER10
0x8a, ; 49 LD CMP10
0xb1, ; 4a LD LSB 1
0x87, ; 4b LD ADR_BUFFER11 ; buffer pointer 1 = 0x0100
0xb5, ; 4c LD LSB 5
0x8b, ; 4d LD CMP11 ; CMP1 = 0x0500
;-------------------------
; Output the command 0x50
;-------------------------
; :start_read_spare_area
0xa1, ; 4e LD MSB 1 ;data_flash port = output
0xb9, ; 4f LD LSB 9 ;DATA_FLASH Port driven by FCI
0x8d, ; 50 LD CTRL_FCI ;PARALLEL Port driven by FCI
; :pre_wait_card_ready
;---------------
0xd0, ; 51 LD A DR_PARALLEL
0x33, ; 52 EXCHANGE
0x28, ; 53 BCLR1 ; test busy line
; JP :pre_wait_card_ready
0x63, ; 54 JP -3
;For 256mb
;-----------
0xa0, ; 55 LD MSB 0
0xb0, ; 56 LD LSB 0
0x8c, ; 57 LD DATA_FLASH
0xba, ; 58 LD LSB 10
0x90, ; 59 LD DR_PARALLEL ; WE = 1, CLE = 0
0xbb, ; 5a LD LSB 11
0x90, ; 5b LD DR_PARALLEL ; WE = 1, CLE = 1
0xb9, ; 5c LD LSB 9
0x90, ; 5d LD DR_PARALLEL ; WE = 0, CLE = 1
0xbb, ; 5e LD LSB 11
0x90, ; 5f LD DR_PARALLEL ; WE = 1, CLE = 1
0xba, ; 60 LD LSB 10
0x90, ; 61 LD DR_PARALLEL ; WE = 1, CLE = 0
;------------------------------------
; Output the 3 or 4 or 5 bytes of address from 0xE5-0xE1
;------------------------------------
0xa0, ; 62 LD MSB 0
0xb1, ; 63 LD LSB 1
0x81, ; 64 LD X ; X = 1
0xae, ; 65 LD MSB 14
0xb6, ; 66 LD LSB 6
0x84, ; 67 LD ADR_BUFFER00 ; buffer pointer 0 = 0x00E6
0xdb, ; 68 LD A DATA_BUFFER0 ; load the number of address bytes
0x82, ; 69 LD Y
0x3c, ; 6a DECY
; LD A ADR_BUFFER01 ; A = 0,256mb
0x26, ; 6b SUB16 ADR_BUFFER0 ; send address from high byte to low byte,256mb
; :loop_send_address
;-----------------
; SUB16 ADR_BUFFER0 ; send address from high byte to low byte
0xdb, ; 6c LD A DATA_BUFFER0
0x8c, ; 6d LD DATA_FLASH
0xa0, ; 6e LD MSB 0
0xbe, ; 6f LD LSB 14
0x90, ; 70 LD DR_PARALLEL ; ALE = 1, WE = 1
0xbc, ; 71 LD LSB 12
0x90, ; 72 LD DR_PARALLEL ; ALE = 1, WE = 0
0xbe, ; 73 LD LSB 14
0x90, ; 74 LD DR_PARALLEL ; ALE = 1, WE = 1
0x26, ; 75 SUB16 ADR_BUFFER0
; LD A DATA_BUFFER0
0x3c, ; 76 DECY
; JP :loop_send_address
0x6b, ; 77 JP -11
0xa0, ; 78 LD MSB 0
0xba, ; 79 LD LSB 10
0x90, ; 7a LD DR_PARALLEL ; ALE = 0, WE = 1
;---------------------------------------------------
;For 256 MB or 2K page send 0x30 command,
;---------------------------------------------------
;send 0x30 cmd
0xa3, ; 7b LD MSB 3
0xb0, ; 7c LD LSB 0
0x8c, ; 7d LD DATA_FLASH
; LD LSB 10
; LD DR_PARALLEL ; WE = 1, CLE = 0
0xbb, ; 7e LD LSB 11
0x90, ; 7f LD DR_PARALLEL ; WE = 1, CLE = 1
0xb9, ; 80 LD LSB 9
0x90, ; 81 LD DR_PARALLEL ; WE = 0, CLE = 1
0xbb, ; 82 LD LSB 11
0x90, ; 83 LD DR_PARALLEL ; WE = 1, CLE = 1
0xba, ; 84 LD LSB 10
0x90, ; 85 LD DR_PARALLEL ; WE = 1, CLE = 0
;--------------
;End for 256mb
;---------------
; :Read_Spare
;------------
0xa0, ; 86 LD MSB 0 ; data_flash port = intput
0xb9, ; 87 LD LSB 9 ; DATA_FLASH Port driven by FCI
0x8d, ; 88 LD CTRL_FCI ; PARALLEL Port driven by FCI
;---------------------
; Read the spare area
;---------------------
; :init_read_spare
0xb2, ; 89 LD LSB 2
0x88, ; 8a LD CMP00 ; CMP00 = 0x02 for toggling RD line
0xb5, ; 8b LD LSB 5
0x82, ; 8c LD Y ; Y = 5
0xae, ; 8d LD MSB 14
0xb7, ; 8e LD LSB 07
0x84, ; 8f LD ADR_BUFFER00 ; ADR0 = 0x00E7, points to spare area
0x89, ; 90 LD CMP01 ; save this address for later use
; :wait_card_ready
;---------------
0xd0, ; 91 LD A DR_PARALLEL
0x33, ; 92 EXCHANGE
0x28, ; 93 BCLR1 ; test busy line
; JP :wait_card_ready
0x63, ; 94 JP -3
; read_spare
;------------
; :read_spare
0xc8, ; 95 LD A CMP00
0x90, ; 96 LD DR_PARALLEL ; RD = 0
0xba, ; 97 LD LSB 10
0x90, ; 98 LD DR_PARALLEL ; RD = 1
0xcc, ; 99 LD A DATA_FLASH ; load DATA_FLASH
0x9b, ; 9a LD DATA_BUFFER0
0x27, ; 9b ADDER16 ADR_BUFFER0
0x3c, ; 9c DECY
; JP :read_spare
0x68, ; 9d JP -8
;-------------------------------
; Check the spare area is valid
;-------------------------------
0xc9, ; 9e LD A CMP01
0x84, ; 9f LD ADR_BUFFER00 ;ADR0 = 0x00E7, points to spare area
0xa0, ; a0 LD MSB 0
0xb5, ; a1 LD LSB 5
0x82, ; a2 LD Y ;6 BYTES TO READ
; :Check_first_6_bytes
;-------------------
0xdb, ; a3 LD A DATA_BUFFER0
0x31, ; a4 XOR ; MASK = 0xFF
0x8, ; a5 CP A=>X ; X = 1
; JP :spare_area_error
0x55, ; a6 JP 21
0x27, ; a7 ADDER16 ADR_BUFFER0 ; Increment pointer
0x3c, ; a8 DECY
; JP :Check_first_6_bytes
0x66, ; a9 JP -6
; :increase_page_address
;------------------------
0xae, ; aa LD MSB 14
0xb4, ; ab LD LSB 4
0x82, ; ac LD Y
0xc0, ; ad LD A <Y>
0x29, ; ae BCLR2 ;if first block is checked
; JP :continue
0x42, ; af JP 2
0x5, ; b0 STATUS STOP
; :continue
0x3c, ; b1 DECY
0xc0, ; b2 LD A <Y> ;0xe3 ->1st row address byte
0x38, ; b3 BSET1 ;If pointer is at 2nd page of the cluster
; JP :increse_cluster_address
0x5c, ; b4 JP 28
0x80, ; b5 LD <Y>
0xae, ; b6 LD MSB 14
0xb2, ; b7 LD LSB 2
0xb, ; b8 CP ALWAYS
0x60, ; b9 BRANCH :check_next_page
; :stop_it2
0x7, ; ba STATUS STOP ERROR
; :spare_area_error
;----------------
; STATUS STOP ERROR
0xae, ; bb LD MSB 14
0xb4, ; bc LD LSB 4
0x82, ; bd LD Y
0xc0, ; be LD A <Y>
0x39, ; bf BSET2 ;if first block is checked
; JP :stop_it2
0x66, ; c0 JP -6
0xa0, ; c1 LD MSB 0
0xb3, ; c2 LD LSB 3
0x82, ; c3 LD Y ;To save 4 adr bytes
0xae, ; c4 LD MSB 14
0xb1, ; c5 LD LSB 1 ; Point to MSB of Physical Addr 0xE1
0x84, ; c6 LD ADR_BUFFER00
; :save_nxt_byte
0xdb, ; c7 LD A DATA_BUFFER0
0x9c, ; c8 LD DATA_BUFFER1
0x2f, ; c9 ADDER16 ADR_BUFFER1
0x27, ; ca ADDER16 ADR_BUFFER0
0x3c, ; cb DECY
; JP :save_nxt_byte
0x65, ; cc JP -5
0xae, ; cd LD MSB 14
0xb3, ; ce LD LSB 3
0x82, ; cf LD Y
; :increse_cluster_address
0xc3, ; d0 LD A MASK
0x84, ; d1 LD ADR_BUFFER00
0xdb, ; d2 LD A DATA_BUFFER0 ;0xff points to cluster size
0x81, ; d3 LD X
0x2, ; d4 CLC
0xc0, ; d5 LD A <Y>
0x28, ; d6 BCLR1
0x25, ; d7 ADDER8 X
0x80, ; d8 LD <Y> ; byte 0 of the address
0x3c, ; d9 DECY ; Y = 0xE2
0xb0, ; da LD LSB 0
0xa0, ; db LD MSB 0
0x81, ; dc LD X ; clear X
0xc0, ; dd LD A <Y>
0x25, ; de ADDER8 X ; byte 1 of the address
0x80, ; df LD <Y>
;Carry at 2nd Row byte -> End of Zone
0xa, ; e0 CP CARRY
; JP :nxt_zone
0x46, ; e1 JP 6
; :check_next_page
;------------------
0xa4, ; e2 LD MSB 4
0xbe, ; e3 LD LSB 14
0xb, ; e4 CP ALWAYS
0x60, ; e5 BRANCH :start_read_spare_area
; :stop_it
0x5, ; e6 STATUS STOP
; :nxt_zone
0xa0, ; e7 LD MSB 0
0xb1, ; e8 LD LSB 1
0x81, ; e9 LD X
0x26, ; ea SUB16 ADR_BUFFER0 ; 0xfe =number of zones
0xdb, ; eb LD A DATA_BUFFER0
0x2, ; ec CLC
0x24, ; ed SUB8 X
0x9, ; ee CP A<X
; JP :stop_it
0x69, ; ef JP -9
; :increase_zone
0x9b, ; f0 LD DATA_BUFFER0
0x3c, ; f1 DECY ;Y = 0xE1 ->Zone adr Byte
0xc0, ; f2 LD A <Y>
0x2, ; f3 CLC
0x25, ; f4 ADDER8 X
0x80, ; f5 LD <Y> ; Move to nxt zone
0xb, ; f6 CP ALWAYS
; JP :check_next_page
0x75, ; f7 JP -21
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