new_smc_dtc_download2562k_end.hex
来自「HID-Ukey底层源码实现（st72651芯片） windows上层驱动」· HEX 代码 · 共 417 行
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// *****************************************************************
// * NOTICE: The information contained in this file is proprietary *
// * to SGS-THOMSON Microelectronics and is being made available *
// * to ST customers under strict non-disclosure agreements. *
// * Use or disclosure of this information is permissible only *
// * under the terms of the existing non-disclosure agreement. *
// *****************************************************************
// Written by Christophe BRICOUT
// Created by MPmanCompiler.exe (v3.0) Thu Oct 13 12:11:14 2005
//============================================================================
//
// SMC DOWNLOAD Plugin
//
//============================================================================
////
//// For Download:
//// 0xE6: Number of address bytes// 3 or 4
//// 0xE5-0xE2: CA0-7, PA0-7, PA8-15, [PA16-23]
//// 0xE0: Page counter. Number of pages to be download
//// 0xF0-0xFF: For the redundant area
////
//// For Erase one block
//// 0xE6: Number of address bytes// 2 or 3
//// 0xE5-0xE3: PA0-7, PA8-15, [PA16-23]
////
//============================================================================
//------------- <<<<<< Entry point for download from buffer0
0xb1, // 0 LD LSB 1
0xb, // 1 CP ALWAYS
// JP :Init_Download
0x42, // 2 JP 2
//------------- <<<<<< Entry point for download from buffer1
0xb3, // 3 LD LSB 3
// :Init_Download
//-------------
0xa0, // 4 LD MSB 0
0x87, // 5 LD ADR_BUFFER11
0xa1, // 6 LD MSB 1 // data_flash port = output,removed for 256mb
0xb9, // 7 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 8 LD CTRL_FCI // PARALLEL Port driven by FCI
0xa0, // 9 LD MSB 0
0xbf, // a LD LSB 15
0x91, // b LD DDR_PARALLEL // PA3-0 as output, PA7-4 as input
0x92, // c LD OR_PARALLEL // PA3=/RD, PA2=ALE, PA1=/WE, PA0=CLE
0xaf, // d LD MSB 15
0x83, // e LD MASK
0x31, // f XOR
0x85, // 10 LD ADR_BUFFER01 // clear the high byte of ADR0
0x86, // 11 LD ADR_BUFFER10 // clear the low byte of ADR1
0x89, // 12 LD CMP01
0x9f, // 13 LD BUFFER_MNGT // Clear segment pointer for calculate PARITY
0xb1, // 14 LD LSB 1
0x81, // 15 LD X // X = 1
0x88, // 16 LD CMP00 // Set CMP0=0x0001 for timeout control on busy
0xba, // 17 LD LSB 10
0x90, // 18 LD DR_PARALLEL // RD = 1// ALE = 0// WE = 1// CLE = 0
//============================================================================
// The buffer flag is in ADR_BUFFER11
// 0x01: write to buf0
// 0x03: write to buf1
// 0x00: erase operation
//============================================================================
// Preset the "Reserved Field", "Data Status Field" & "Block Status Byte"
0xaf, // 19 LD MSB 15
0xb0, // 1a LD LSB 0
0x84, // 1b LD ADR_BUFFER00 // ADR0 points to spare area
0xba, // 1c LD LSB 10
0x82, // 1d LD Y // Used to count 6 time of ADR0 pointer
0xc3, // 1e LD A MASK
// :Preset_0xFF
//-----------
0x9b, // 1f LD DATA_BUFFER0
0x27, // 20 ADDER16 ADR_BUFFER0
0x3d, // 21 INCY
// JP :Preset_0xFF
0x63, // 22 JP -3
0xaf, // 23 LD MSB 15
0xbc, // 24 LD LSB 12
0x82, // 25 LD Y // Y points to low byte of Address Field-2
////// Calculate the parity bit of the address fields
////// Since ST7 is too slow to do this job, let DTC do it!!
0xdb, // 26 LD A DATA_BUFFER0
0x27, // 27 ADDER16 ADR_BUFFER0
0x1, // 28 SEC
0x31, // 29 XOR
0xdb, // 2a LD A DATA_BUFFER0
0x31, // 2b XOR
0xa, // 2c CP CARRY
// JP :Loop_Write_Pages
0x45, // 2d JP 5
0x31, // 2e XOR
0x38, // 2f BSET1 // Set the parity bit
0x9b, // 30 LD DATA_BUFFER0 // Update parity bit of Address-Field 1
0x80, // 31 LD <Y> // Update parity bit of Address-Field 2
//----------------
// :Loop_Write_Pages
//----------------
0xba, // 32 LD LSB 10
0x90, // 33 LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 0
//// Keep CLE as high to output "Data Input" or "Block Erase" command
//============================================================================
0xa1, // 34 LD MSB 1 // data_flash port = output
0xb9, // 35 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 36 LD CTRL_FCI // PARALLEL Port driven by FCI
0xa8, // 37 LD MSB 8
0xb0, // 38 LD LSB 0
0x8c, // 39 LD DATA_FLASH // Send the first command. It is 0x80 or 0x60
0xbb, // 3a LD LSB 11
0x90, // 3b LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 1
0xb9, // 3c LD LSB 9
0x90, // 3d LD DR_PARALLEL // RD = 1, ALE = 0, WE = 0, CLE = 1
0xbb, // 3e LD LSB 11
0x90, // 3f LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 1
0xba, // 40 LD LSB 10
0x90, // 41 LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 0
//============================================================================
//// Finish output a command, set CLE low.
//// Going to output the address, set ALE high
0xbe, // 42 LD LSB 14
0x90, // 43 LD DR_PARALLEL // RD = 1, ALE = 1, WE = 1, CLE = 0
0xae, // 44 LD MSB 14
0xb6, // 45 LD LSB 6
0x84, // 46 LD ADR_BUFFER00 // ADR0 = 0x00E6// points to "Num of address"
0xdb, // 47 LD A DATA_BUFFER0
0x82, // 48 LD Y // Load number of addres bytes
0x26, // 49 SUB16 ADR_BUFFER0
0x3c, // 4a DECY
// :Send_Address_Bytes
0xdb, // 4b LD A DATA_BUFFER0
0x26, // 4c SUB16 ADR_BUFFER0
0x8c, // 4d LD DATA_FLASH // Send the address byte
0xbc, // 4e LD LSB 12
0x90, // 4f LD DR_PARALLEL // RD = 1, ALE = 1, WE = 0, CLE = 0
0xbe, // 50 LD LSB 14
0x90, // 51 LD DR_PARALLEL // RD = 1, ALE = 1, WE = 1, CLE = 0
0x3c, // 52 DECY
// JP :Send_Address_Bytes
0x68, // 53 JP -8
0xba, // 54 LD LSB 10
0x90, // 55 LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 0
//============================================================================
// :write_next_col
//-------------- // Reset the ECC machine first
0xa3, // 56 LD MSB 3 // Reset ECC machine, DATA_FLASH port = output
0xb9, // 57 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 58 LD CTRL_FCI // PARALLEL Port driven by FCI
0xc9, // 59 LD A CMP01
0x82, // 5a LD Y
0xaf, // 5b LD MSB 15
0xbd, // 5c LD LSB 13
0x84, // 5d LD ADR_BUFFER00 // Load pointer of ECC1 (0x00FD)
//============================================================================
//// Wait on one of the buffer full
//commented for debug
0xc7, // 5e LD A ADR_BUFFER11
0x39, // 5f BSET2
// JP :Wait_Buffer1_Full
0x45, // 60 JP 5
// :Wait_Buffer0_Full
0xdf, // 61 LD A BUFFER_MNGT
0x2a, // 62 BCLR3
// JP :Wait_Buffer0_Full
0x62, // 63 JP -2
// JP :Write_256_Bytes
0x44, // 64 JP 4
// :Wait_Buffer1_Full
0xdf, // 65 LD A BUFFER_MNGT
0x2b, // 66 BCLR4
// JP :Wait_Buffer1_Full
0x62, // 67 JP -2
//============================================================================
// :Write_256_Bytes
//---------------
0xdc, // 68 LD A DATA_BUFFER1
0x8c, // 69 LD DATA_FLASH
0x9d, // 6a LD ECC_CRC
0xdd, // 6b LD A ECC_CRC // AUTO UPDATE OF Line PARITY 1
0xdd, // 6c LD A ECC_CRC // AUTO UPDATE OF Line PARITY 2
0xdd, // 6d LD A ECC_CRC // AUTO UPDATE OF column PARITY
0xb8, // 6e LD LSB 8
0x90, // 6f LD DR_PARALLEL // WE = 0
0xba, // 70 LD LSB 10
0x90, // 71 LD DR_PARALLEL // WE = 1
0x2f, // 72 ADDER16 ADR_BUFFER1
0x3d, // 73 INCY
// JP :Write_256_Bytes
0x6c, // 74 JP -12
// Save the ECC code
//------------------
0xde, // 75 LD A TMP_ECC // first read (Line parity 1)
0x9b, // 76 LD DATA_BUFFER0
0xdd, // 77 LD A ECC_CRC // -- INCR CRC_ECC_STATE --
0x27, // 78 ADDER16 ADR_BUFFER0
0xde, // 79 LD A TMP_ECC // second read (Line parity 2)
0x9b, // 7a LD DATA_BUFFER0
0xdd, // 7b LD A ECC_CRC // -- INCR CRC_ECC_STATE --
0x27, // 7c ADDER16 ADR_BUFFER0
0xde, // 7d LD A TMP_ECC // third read ( column parity)
0x9b, // 7e LD DATA_BUFFER0
0xaf, // 7f LD MSB 15
0xb8, // 80 LD LSB 8
0x84, // 81 LD ADR_BUFFER00 // Load pointer of ECC2 (0x00F8)
0xc7, // 82 LD A ADR_BUFFER11 // Write buf0: 0001=>0010, =>0011
0x28, // 83 BCLR1
// JP :Write_256_Bytes
0x7c, // 84 JP -28
//============================================================================
//// Write 16 bytes of the redundant area
0xaf, // 85 LD MSB 15
0xb0, // 86 LD LSB 0
0x82, // 87 LD Y // Y = 0xF0// pointer of redundant area (0x00F0)
// :Write_Spare_Area
//----------------
0xc0, // 88 LD A <Y>
0x8c, // 89 LD DATA_FLASH
0xb8, // 8a LD LSB 8
0x90, // 8b LD DR_PARALLEL // WE = 0
0xba, // 8c LD LSB 10
0x90, // 8d LD DR_PARALLEL // WE = 1
0x3d, // 8e INCY
// JP :Write_Spare_Area
0x67, // 8f JP -7
//-----------------------------------------------------------------
//testing
//----------------------------------------------------------------
// :Release_Buffer
//--------------
0xc7, // 90 LD A ADR_BUFFER11 // Buf0: 0001=>0010=>0011
0x2a, // 91 BCLR3 // Wrap the segment pointer
0x87, // 92 LD ADR_BUFFER11 // Reload for the next page writing
// JP :Free_Buffer0
0x43, // 93 JP 3
0xb2, // 94 LD LSB 2
// JP :Free_Buffer
0x42, // 95 JP 2
// :Free_Buffer0
//------------
0xb1, // 96 LD LSB 1
// :Free_Buffer
//-----------
0x9f, // 97 LD BUFFER_MNGT
0xb0, // 98 LD LSB 0
0x9f, // 99 LD BUFFER_MNGT
//-------------
//For 256MB
//-------------
0xae, // 9a LD MSB 14
0xb0, // 9b LD LSB 0
0x84, // 9c LD ADR_BUFFER00 //point to 0xe0
0xdb, // 9d LD A DATA_BUFFER0
0x2, // 9e CLC
0x24, // 9f SUB8 X
0x9b, // a0 LD DATA_BUFFER0
0x9, // a1 CP A<X
// JP :pgm_page
0x52, // a2 JP 18
0xae, // a3 LD MSB 14
0xb4, // a4 LD LSB 4
0x84, // a5 LD ADR_BUFFER00
0xa0, // a6 LD MSB 0
0xb2, // a7 LD LSB 2
0x82, // a8 LD Y
0xdb, // a9 LD A DATA_BUFFER0
0x2, // aa CLC
0x2d, // ab ADDER8 Y
0x2b, // ac BCLR4
0x9b, // ad LD DATA_BUFFER0
0xa5, // ae LD MSB 5
0xb6, // af LD LSB 6
0x60, // b0 BRANCH :write_next_col
0xc5, // b1 LD A ADR_BUFFER01
0x27, // b2 ADDER16 ADR_BUFFER0 //Reload both 0xe5 and 0xe4 for nxt page
0x9b, // b3 LD DATA_BUFFER0
//============================================================================
// :pgm_page
0xa1, // b4 LD MSB 1 // Send the "Page Program" command - 0x10
0xb0, // b5 LD LSB 0
0x8c, // b6 LD DATA_FLASH
0xbb, // b7 LD LSB 11
0x90, // b8 LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 1
0xb9, // b9 LD LSB 9
0x90, // ba LD DR_PARALLEL // RD = 1, ALE = 0, WE = 0, CLE = 1
0xbb, // bb LD LSB 11
0x90, // bc LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 1
0xba, // bd LD LSB 10
0x90, // be LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 0,
//============================================================================
//// Wait on busy line
//============================================================================
// :Wait_On_Busy
0x0, // bf NOP
0xd0, // c0 LD A DR_PARALLEL
0x33, // c1 EXCHANGE
0x28, // c2 BCLR1 // Test R/-B line
// JP :Wait_On_Busy
0x64, // c3 JP -4
//============================================================================
//// Read the status byte
0xa7, // c4 LD MSB 7
0xb0, // c5 LD LSB 0
0x8c, // c6 LD DATA_FLASH // Send "Status Read" command
0xbb, // c7 LD LSB 11
0x90, // c8 LD DR_PARALLEL // RD = 1, ALE = 0, WE = 0, CLE = 1
0xb9, // c9 LD LSB 9
0x90, // ca LD DR_PARALLEL // RD = 1, ALE = 0, WE = 0, CLE = 1
0xbb, // cb LD LSB 11
0x90, // cc LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 1
0xba, // cd LD LSB 10
0x90, // ce LD DR_PARALLEL // RD = 1, ALE = 0, WE = 1, CLE = 0
0xa0, // cf LD MSB 0 // DATA_FLASH port = input
0xb9, // d0 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // d1 LD CTRL_FCI // PARALLEL Port driven by FCI
0xb2, // d2 LD LSB 2
0x90, // d3 LD DR_PARALLEL // WE = 1, CLE = 0, ALE = 0, RD = 0
0xba, // d4 LD LSB 10
0x90, // d5 LD DR_PARALLEL // WE = 1, CLE = 0, ALE = 0, RD = 1
0xcc, // d6 LD A DATA_FLASH // Get the status byte
0x28, // d7 BCLR1
// JP :Status_Good
0x42, // d8 JP 2
0x7, // d9 STATUS ERROR STOP // Status "FAIL" Stop the DTC
//============================================================================
// :Status_Good
0xc7, // da LD A ADR_BUFFER11 // Buf0: 0001=>0010=>0011
0x38, // db BSET1
// JP :increment_page
0x42, // dc JP 2
0x5, // dd STATUS STOP // Return if it is a BLOCK_ERASE
//============================================================================
// :increment_page
//// Decrease the page number and increase the page address
0xc9, // de LD A CMP01
0x85, // df LD ADR_BUFFER01
0xae, // e0 LD MSB 14
0xb3, // e1 LD LSB 3
0x84, // e2 LD ADR_BUFFER00 //0xe5 = 1st col. byte
// :next_page
0xdb, // e3 LD A DATA_BUFFER0
0x2, // e4 CLC
0x25, // e5 ADDER8 X
0x9b, // e6 LD DATA_BUFFER0
// :dec_page
0xae, // e7 LD MSB 14
0xb0, // e8 LD LSB 0
0x82, // e9 LD Y
0xc0, // ea LD A <Y>
0x8, // eb CP A=>X
0xa3, // ec LD MSB 3
0xb2, // ed LD LSB 2
0x60, // ee BRANCH :Loop_Write_Pages
0x5, // ef STATUS STOP
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