📄 smc_dtc_copypages256_end_old.hex
字号:
// *****************************************************************
// * NOTICE: The information contained in this file is proprietary *
// * to SGS-THOMSON Microelectronics and is being made available *
// * to ST customers under strict non-disclosure agreements. *
// * Use or disclosure of this information is permissible only *
// * under the terms of the existing non-disclosure agreement. *
// *****************************************************************
// Written by Christophe BRICOUT
// Created by MPmanCompiler.exe (v3.0) Fri Mar 28 04:55:47 2003
//===================================================================
//
// SMART MEDIA CARD
//
//===================================================================
//----------------------
// dtc_smc_copy_page.fsm
//----------------------
//--------------------------
//init_write_number_of_block
//--------------------------
0xa0, // 0 LD MSB 0
0xb1, // 1 LD LSB 1
0x81, // 2 LD X // X<=1
0xb0, // 3 LD LSB 0
0x85, // 4 LD ADR_BUFFER01
0x88, // 5 LD CMP00
0x9f, // 6 LD BUFFER_MNGT
//-----------------
//init_dtc_ctrl_reg
//-----------------
0xa1, // 7 LD MSB 1 // data_flash port = output
0xb9, // 8 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 9 LD CTRL_FCI // PARALLEL Port driven by FCI
//-------------------------------
//command_latch_cycle (Read1 CMD)
//-------------------------------
//LD MSB 0
//LD LSB 0
0xc5, // a LD A ADR_BUFFER01
0x8c, // b LD DATA_FLASH
//LD MSB 0
0xba, // c LD LSB 10
0x90, // d LD DR_PARALLEL
0xbb, // e LD LSB 11
0x90, // f LD DR_PARALLEL
0xb9, // 10 LD LSB 9
0x90, // 11 LD DR_PARALLEL
0xbb, // 12 LD LSB 11
0x90, // 13 LD DR_PARALLEL
//send address, set ALE high
//------------------------------
0xbe, // 14 LD LSB 14
0x90, // 15 LD DR_PARALLEL
//-------------------------
// read_address_latch_cycle
//-------------------------
//read_address_latch_cycle_nb_Bytes
//---------------------------------
0xae, // 16 LD MSB 14
0xb6, // 17 LD LSB 06
0x84, // 18 LD ADR_BUFFER00 // buffer pointer 0 = 0x00E6
0xdb, // 19 LD A DATA_BUFFER0
0x82, // 1a LD Y // Y = number of address bytes
// LD CMP10 //save address bytes
0x3c, // 1b DECY
// LD LSB 12
// LD CMP01 // CMP01 = 12, for send address toggling lines
// LD LSB 14
// LD DR_PARALLEL // ALE = 1, WE = 1
0x26, // 1c SUB16 ADR_BUFFER0 // send address from high byte to low byte
// :loop_send_address
//-----------------
// SUB16 ADR_BUFFER0 // send address from high byte to low byte
0xdb, // 1d LD A DATA_BUFFER0
0x8c, // 1e LD DATA_FLASH // Output the address bytes
0xbc, // 1f LD LSB 12
0x90, // 20 LD DR_PARALLEL // ALE = 1, WE = 0
0xbe, // 21 LD LSB 14
0x90, // 22 LD DR_PARALLEL // ALE = 1, WE = 1
0x26, // 23 SUB16 ADR_BUFFER0 // send address from high byte to low byte
// LD A DATA_BUFFER0
0x3c, // 24 DECY
// JP :loop_send_address
0x68, // 25 JP -8
0xa0, // 26 LD MSB 0
0xba, // 27 LD LSB 10
0x90, // 28 LD DR_PARALLEL // ALE = 0, WE = 1
//end of send address
//---------------------
//wait_read1_addr_ready
//---------------------
0xa3, // 29 LD MSB 3
0xb5, // 2a LD LSB 5
0x8c, // 2b LD DATA_FLASH
0xa0, // 2c LD MSB 0
//LD LSB 10
//LD DR_PARALLEL
0xbb, // 2d LD LSB 11
0x90, // 2e LD DR_PARALLEL
0xb9, // 2f LD LSB 9
0x90, // 30 LD DR_PARALLEL
0xbb, // 31 LD LSB 11
0x90, // 32 LD DR_PARALLEL
0xba, // 33 LD LSB 10
0x90, // 34 LD DR_PARALLEL
//removed time-out for optimizing
//--------------------------------
//init_timeout
//------------
//LD LSB 00
//LD ADR_BUFFER01 // buffer 0 address ( 8..15 )
//LD ADR_BUFFER00 // buffer 0 address ( 0..7 )
//LD CMP00
//LD MSB 15
//LD CMP01
// :wait_read1_addr_ready
//---------------------
//ADDER16 ADR_BUFFER0
//CP ADR_BUFFER0<CMP0
//JP :read1_addr_no_timeout
//STATUS STOP ERROR // timeout >20ms
//NOP
//NOP
0x0, // 35 NOP
0x0, // 36 NOP
//:read1_addr_no_timeout
//---------------------
0xd0, // 37 LD A DR_PARALLEL
0x33, // 38 EXCHANGE
0x28, // 39 BCLR1 //test R/B
// JP :wait_read1_addr_ready
0x65, // 3a JP -5
//send next command for copy operation 0x85
//-------------------------------------------
0xa8, // 3b LD MSB 8
0xb5, // 3c LD LSB 5
0x8c, // 3d LD DATA_FLASH
0xa0, // 3e LD MSB 0
//LD LSB 10
//LD DR_PARALLEL
0xbb, // 3f LD LSB 11
0x90, // 40 LD DR_PARALLEL
0xb9, // 41 LD LSB 9
0x90, // 42 LD DR_PARALLEL
0xbb, // 43 LD LSB 11
0x90, // 44 LD DR_PARALLEL
//send address bytes
0xbe, // 45 LD LSB 14
0x90, // 46 LD DR_PARALLEL
//send the address of destination block
//--------------------------------------
// :send_address
//-------------
0xae, // 47 LD MSB 14
0xb6, // 48 LD LSB 06
0x84, // 49 LD ADR_BUFFER00 // buffer pointer 0 = 0x00E6
0xdb, // 4a LD A DATA_BUFFER0
0x82, // 4b LD Y // Y = number of address bytes
0x3c, // 4c DECY
// LD LSB 12
// LD CMP01 // CMP01 = 12, for send address toggling lines
// LD LSB 14
// LD DR_PARALLEL // ALE = 1, WE = 1
0x27, // 4d ADDER16 ADR_BUFFER0 // send address from high byte to low byte
// :loop_send_address1
//-----------------
// SUB16 ADR_BUFFER0 // send address from high byte to low byte
0xdb, // 4e LD A DATA_BUFFER0
0x8c, // 4f LD DATA_FLASH // Output the address bytes
0xbc, // 50 LD LSB 12
0x90, // 51 LD DR_PARALLEL // ALE = 1, WE = 0
0xbe, // 52 LD LSB 14
0x90, // 53 LD DR_PARALLEL // ALE = 1, WE = 1
0x27, // 54 ADDER16 ADR_BUFFER0 // send address from high byte to low byte
// LD A DATA_BUFFER0
0x3c, // 55 DECY
// JP :loop_send_address1
0x68, // 56 JP -8
// LD MSB 0
0xba, // 57 LD LSB 10
0x90, // 58 LD DR_PARALLEL // ALE = 0, WE = 1
//end of send address
//---------------------
//chk if the first page is not from the start of coloumn
//-------------------------------------------------------
//chk the flag set in the 0xfd to get the no. of blocks
//-------------------------------------------------------
0xaf, // 59 LD MSB 15
0xbd, // 5a LD LSB 13
0x84, // 5b LD ADR_BUFFER00
0xc5, // 5c LD A ADR_BUFFER01
0x87, // 5d LD ADR_BUFFER11
0x86, // 5e LD ADR_BUFFER10 //ADR1 = 0x0000
0xdb, // 5f LD A DATA_BUFFER0
0x27, // 60 ADDER16 ADR_BUFFER0
0x27, // 61 ADDER16 ADR_BUFFER0 //point ADR0 = 0x00ff
0x38, // 62 BSET1
// JP :chk_nxt_bit
0x45, // 63 JP 5
0x39, // 64 BSET2
// JP :2_block_ff
0x4a, // 65 JP 10
0xb, // 66 CP ALWAYS
// JP :start_pgm_cycle
0x5a, // 67 JP 26
// :chk_nxt_bit
0x39, // 68 BSET2
// JP :3_block_ff
0x4a, // 69 JP 10
// :1_block_ff
//--------------
0xb2, // 6a LD LSB 2
0x8b, // 6b LD CMP11 //only one block so CMP1 = 0x210 = 528 bytes
0xa1, // 6c LD MSB 1
0xb, // 6d CP ALWAYS
// JP :send_ff
0x48, // 6e JP 8
// :2_block_ff
//------------
0xb4, // 6f LD LSB 4
0x8b, // 70 LD CMP11
0xa2, // 71 LD MSB 2
//CP ALWAYS
// JP :send_ff
0x44, // 72 JP 4
// :3_block_ff
//-----------
0xb6, // 73 LD LSB 6
0x8b, // 74 LD CMP11
0xa3, // 75 LD MSB 3 //CMP1 = 0x630
// :send_ff
0xb0, // 76 LD LSB 0
0x8a, // 77 LD CMP10
//write data on to page, generate 528 write pulses
//------------------------------------------------
//:gen_more_pulses
//---------------
// :write_dat_sec
//-------------
0xc4, // 78 LD A ADR_BUFFER00
0x8c, // 79 LD DATA_FLASH
0xb8, // 7a LD LSB 8
0x90, // 7b LD DR_PARALLEL
0xba, // 7c LD LSB 10
0x90, // 7d LD DR_PARALLEL
0x2f, // 7e ADDER16 ADR_BUFFER1
0xf, // 7f CP ADR_BUFFER1<CMP1
// JP :write_dat_sec
0x68, // 80 JP -8
//----------------------------
// :Page_Pgm_command_latch_cycle
//----------------------------
// :start_pgm_cycle
//----------------
0xa1, // 81 LD MSB 1
0xb0, // 82 LD LSB 0
0x8c, // 83 LD DATA_FLASH
0xa0, // 84 LD MSB 0
//LD LSB 10
//LD DR_PARALLEL
0xbb, // 85 LD LSB 11
0x90, // 86 LD DR_PARALLEL
0xb9, // 87 LD LSB 9
0x90, // 88 LD DR_PARALLEL
0xbb, // 89 LD LSB 11
0x90, // 8a LD DR_PARALLEL
0xba, // 8b LD LSB 10
0x90, // 8c LD DR_PARALLEL
//---------------------------
// read_status & check_status
//---------------------------
//wait_card_ready
//---------------
//init_timeout
//------------
//LD LSB 00
//LD ADR_BUFFER11
//LD ADR_BUFFER10
//LD CMP10
//LD MSB 15
//LD CMP11
// :wait_card_ready
//---------------
//ADDER16 ADR_BUFFER1
//CP ADR_BUFFER1<CMP1
//JP :no_timeout
//STATUS STOP ERROR // timeout 20ms
//:no_timeout
//----------
0x0, // 8d NOP
0x0, // 8e NOP
0xd0, // 8f LD A DR_PARALLEL
0x33, // 90 EXCHANGE
0x28, // 91 BCLR1 //test R/B
// JP :wait_card_ready
0x65, // 92 JP -5
// :read_status_command_latch_cycle
//-------------------------------
0xa7, // 93 LD MSB 7
0xb0, // 94 LD LSB 0
0x8c, // 95 LD DATA_FLASH
0xa0, // 96 LD MSB 0
//LD LSB 10
//LD DR_PARALLEL
0xbb, // 97 LD LSB 11
0x90, // 98 LD DR_PARALLEL
0xb9, // 99 LD LSB 9
0x90, // 9a LD DR_PARALLEL
0xbb, // 9b LD LSB 11
0x90, // 9c LD DR_PARALLEL
0xba, // 9d LD LSB 10
0x90, // 9e LD DR_PARALLEL
// :init_read_status_seq
//---------------------
//LD MSB 0
0xb9, // 9f LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // a0 LD CTRL_FCI // PARALLEL Port driven by FCI
// :read_status_seq
//----------------
//LD MSB 0
0xb2, // a1 LD LSB 2
0x90, // a2 LD DR_PARALLEL
//NOP
0xba, // a3 LD LSB 10
0x90, // a4 LD DR_PARALLEL
0xcc, // a5 LD A DATA_FLASH // load DATA_FLASH
// :check_status
//-------------
//EXCHANGE
0x28, // a6 BCLR1
// JP :no_error
0x42, // a7 JP 2
//BCLR4
//JP :error_status
//CP A<X
//JP :no_error
// :error_status
//------------
0x7, // a8 STATUS ERROR STOP
// :no_error
//--------
//LD MSB 0
//------------
//end_of_block
//------------
//For 256mb
0xdb, // a9 LD A DATA_BUFFER0 //ADR0 = 0x00ff, contains 2K page pointer
0x8, // aa CP A=>X
// JP :dec_512_page
0x42, // ab JP 2
// :stop
0x5, // ac STATUS STOP //if 0 then stop
// :dec_512_page
//----------------
0xa0, // ad LD MSB 0
0xb4, // ae LD LSB 4
0x82, // af LD Y
0x26, // b0 SUB16 ADR_BUFFER0
0xdb, // b1 LD A DATA_BUFFER0
0x2, // b2 CLC
0x2c, // b3 SUB8 Y //decrement by 4
0x9b, // b4 LD DATA_BUFFER0
//add new
//-------------------------------------------------
//:increment_page
//---------------
//// Decrease the page number and increase the page address
0xae, // b5 LD MSB 14
0xb3, // b6 LD LSB 3
0x82, // b7 LD Y
// :next_page
//-----------------------------------
0xc0, // b8 LD A <Y>
0x2, // b9 CLC
0x25, // ba ADDER8 X
0x80, // bb LD <Y> // Increase the page address and save it back
0xae, // bc LD MSB 14
0xb9, // bd LD LSB 9
0x82, // be LD Y
0xc0, // bf LD A <Y>
0x2, // c0 CLC
0x25, // c1 ADDER8 X
0x80, // c2 LD <Y>
0x3c, // c3 DECY //Y = 0xe8
// LD MSB 0
// LD LSB 0
// BRANCH
// JP :end_of_page
0x5f, // c4 JP 31
// :last_page
//---------------
0x26, // c5 SUB16 ADR_BUFFER0 //ADR0 =0xfe
0xdb, // c6 LD A DATA_BUFFER0
//CP A=>X
0x9, // c7 CP A<X
//JP :partial_page_pgm
// JP :stop
0x7c, // c8 JP -28
//STATUS STOP
// :partial_page_pgm
//-----------------
0x26, // c9 SUB16 ADR_BUFFER0 //ADR0 = 0xfd
0x38, // ca BSET1
// JP :chk_nxtbit
0x43, // cb JP 3
0x39, // cc BSET2
// JP :2_block_extra
0x4a, // cd JP 10
// :chk_nxtbit
0x39, // ce BSET2
// JP :1_block_extra
0x4e, // cf JP 14
// :3_block_extra
0xb3, // d0 LD LSB 3
0x9b, // d1 LD DATA_BUFFER0
0xb2, // d2 LD LSB 2
0x8b, // d3 LD CMP11 //col 1
0xa1, // d4 LD MSB 1
0xb, // d5 CP ALWAYS
// JP :end1
0x46, // d6 JP 6
// :2_block_extra
0xb2, // d7 LD LSB 2
0x9b, // d8 LD DATA_BUFFER0 //
0xb4, // d9 LD LSB 4
0x8b, // da LD CMP11 //col 1
0xa2, // db LD MSB 2
//CP ALWAYS //if, then else
// :end1
// JP :end
0x5a, // dc JP 26
// :1_block_extra
0xb1, // dd LD LSB 1
0x9b, // de LD DATA_BUFFER0
0xb6, // df LD LSB 6
0x8b, // e0 LD CMP11 //col 1
0xa3, // e1 LD MSB 3
//new
//CP ALWAYS //commented for if then else
// JP :end
0x54, // e2 JP 20
//:end
//LD LSB 0
//LD CMP10
//LD A CMP11
//LD <Y>
//DECY
//LD A CMP10
//LD <Y>
//ADDER16 ADR_BUFFER0 //0xfe need not to be reseted now
//CP ALWAYS
//JP :process_continue
// :end_of_page
//-------------
0x27, // e3 ADDER16 ADR_BUFFER0
0xdb, // e4 LD A DATA_BUFFER0
0x2, // e5 CLC
0x24, // e6 SUB8 X
0x9b, // e7 LD DATA_BUFFER0 //decrement 0xff by 1 => decrement of 2k page no.
0x9, // e8 CP A<X
0xac, // e9 LD MSB 12
0xb5, // ea LD LSB 5
0x60, // eb BRANCH
//JP :last_page
0xc5, // ec LD A ADR_BUFFER01 //0xe8, col add2
0x80, // ed LD <Y>
0x3c, // ee DECY
0x80, // ef LD <Y> //Y=0xe7, col add1
0x26, // f0 SUB16 ADR_BUFFER0 // ADR0 = 0xfd, flag for col. no.
0x26, // f1 SUB16 ADR_BUFFER0 // ADR0 = 0xfe, flag for col. no.
// :process_continue
0xc5, // f2 LD A ADR_BUFFER01
0x9b, // f3 LD DATA_BUFFER0 //reset it to 0
0xb, // f4 CP ALWAYS
0x60, // f5 BRANCH :start
// :end
0xb0, // f6 LD LSB 0
0x8a, // f7 LD CMP10
0xcb, // f8 LD A CMP11
0x80, // f9 LD <Y>
0x3c, // fa DECY
0xca, // fb LD A CMP10
0x80, // fc LD <Y>
0x27, // fd ADDER16 ADR_BUFFER0 //0xfe need not to be reseted now
0xb, // fe CP ALWAYS
// JP :process_continue
0x6d, // ff JP -13
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -