📄 smc_dtc_mark_pages_end.hex
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// *****************************************************************
// * NOTICE: The information contained in this file is proprietary *
// * to SGS-THOMSON Microelectronics and is being made available *
// * to ST customers under strict non-disclosure agreements. *
// * Use or disclosure of this information is permissible only *
// * under the terms of the existing non-disclosure agreement. *
// *****************************************************************
// Written by Christophe BRICOUT
// Created by MPmanCompiler.exe (v3.0) Wed Apr 07 18:45:56 2004
//===================================================================
//
// SMART MEDIA CARD
//
//===================================================================
//----------------------
// dtc_smc_copy_page.fsm
//----------------------
//--------------------------
//init_write_number_of_block
//--------------------------
0xa0, // 0 LD MSB 0
0xb1, // 1 LD LSB 1
0x81, // 2 LD X // X<=1
//-----------------
//init_dtc_ctrl_reg
//-----------------
0xa1, // 3 LD MSB 1 // data_flash port = output
0xb9, // 4 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 5 LD CTRL_FCI // PARALLEL Port driven by FCI
//-------------------------------
//command_latch_cycle (Read2 CMD)
//-------------------------------
0xa5, // 6 LD MSB 5
0xb0, // 7 LD LSB 0
0x8c, // 8 LD DATA_FLASH
0xa0, // 9 LD MSB 0
0xba, // a LD LSB 10
0x90, // b LD DR_PARALLEL
0xbb, // c LD LSB 11
0x90, // d LD DR_PARALLEL
0xb9, // e LD LSB 9
0x90, // f LD DR_PARALLEL
0xbb, // 10 LD LSB 11
0x90, // 11 LD DR_PARALLEL
0xba, // 12 LD LSB 10
0x90, // 13 LD DR_PARALLEL
//-----------------
//init_dtc_ctrl_reg
//-----------------
0xa1, // 14 LD MSB 1 // data_flash port = output
0xb9, // 15 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 16 LD CTRL_FCI // PARALLEL Port driven by FCI
//-------------------------------
//command_latch_cycle (SDI CMD)
//-------------------------------
0xa8, // 17 LD MSB 8
0xb0, // 18 LD LSB 0
0x8c, // 19 LD DATA_FLASH
0xa0, // 1a LD MSB 0
0xba, // 1b LD LSB 10
0x90, // 1c LD DR_PARALLEL
0xbb, // 1d LD LSB 11
0x90, // 1e LD DR_PARALLEL
0xb9, // 1f LD LSB 9
0x90, // 20 LD DR_PARALLEL
0xbb, // 21 LD LSB 11
0x90, // 22 LD DR_PARALLEL
0xba, // 23 LD LSB 10
0x90, // 24 LD DR_PARALLEL
//-------------------------
// read_address_latch_cycle
//-------------------------
//read_address_latch_cycle_nb_Bytes
//---------------------------------
0xa0, // 25 LD MSB 0
0xb0, // 26 LD LSB 0
0x85, // 27 LD ADR_BUFFER01 // buffer 0 address ( 15..8 )
0xae, // 28 LD MSB 14
0xb6, // 29 LD LSB 06
0x84, // 2a LD ADR_BUFFER00 // buffer 0 address ( 0..7 )
0xdb, // 2b LD A DATA_BUFFER0
0x82, // 2c LD Y
0xae, // 2d LD MSB 14
0xb2, // 2e LD LSB 02
0x84, // 2f LD ADR_BUFFER00
0xa0, // 30 LD MSB 0
0xba, // 31 LD LSB 10
0x90, // 32 LD DR_PARALLEL
0xbe, // 33 LD LSB 14
0x90, // 34 LD DR_PARALLEL
// read_loop_send_address
// -----------------
// :read_loop_send_address
0xdb, // 35 LD A DATA_BUFFER0
0x8c, // 36 LD DATA_FLASH
0xa0, // 37 LD MSB 0
0xbc, // 38 LD LSB 12
0x90, // 39 LD DR_PARALLEL
0xbe, // 3a LD LSB 14
0x90, // 3b LD DR_PARALLEL
0x27, // 3c ADDER16 ADR_BUFFER0
0x3c, // 3d DECY
0xc2, // 3e LD A Y
0x8, // 3f CP A=>X
// JP :read_loop_send_address
0x6b, // 40 JP -11
0xba, // 41 LD LSB 10
0x90, // 42 LD DR_PARALLEL
//---------------------
//wait_sdi_addr_ready
//---------------------
//init_timeout
//------------
0xb0, // 43 LD LSB 00
0x85, // 44 LD ADR_BUFFER01 // buffer 0 address ( 8..15 )
0x84, // 45 LD ADR_BUFFER00 // buffer 0 address ( 0..7 )
0x88, // 46 LD CMP00
0xaf, // 47 LD MSB 15
0x89, // 48 LD CMP01
// :wait_sdi_addr_ready
//---------------------
0x27, // 49 ADDER16 ADR_BUFFER0
0xd, // 4a CP ADR_BUFFER0<CMP0
// JP :sdi_addr_no_timeout
0x42, // 4b JP 2
0x7, // 4c STATUS STOP ERROR // timeout >20ms
// :sdi_addr_no_timeout
//---------------------
0xd0, // 4d LD A DR_PARALLEL
0x33, // 4e EXCHANGE
0x28, // 4f BCLR1 //test R/B
// JP :wait_sdi_addr_ready
0x67, // 50 JP -7
//------------
// write_spare
//------------
//init_write_spare
//----------------
0xa0, // 51 LD MSB 0
0xb0, // 52 LD LSB 0
0x85, // 53 LD ADR_BUFFER01 // buffer 0 address ( 15..8 )
0x89, // 54 LD CMP01
0xae, // 55 LD MSB 14
0xb7, // 56 LD LSB 07
0x84, // 57 LD ADR_BUFFER00
0xaf, // 58 LD MSB 15
0x88, // 59 LD CMP00
// :write_spare
//-----------
0xdb, // 5a LD A DATA_BUFFER0
0x8c, // 5b LD DATA_FLASH
0xa0, // 5c LD MSB 0
0xb8, // 5d LD LSB 8
0x90, // 5e LD DR_PARALLEL
0xba, // 5f LD LSB 10
0x90, // 60 LD DR_PARALLEL
0x27, // 61 ADDER16 ADR_BUFFER0
0xd, // 62 CP ADR_BUFFER0<CMP0
// JP :write_spare
0x69, // 63 JP -9
//----------------------------
// :Page_Pgm_command_latch_cycle
//----------------------------
0xa1, // 64 LD MSB 1
0xb0, // 65 LD LSB 0
0x8c, // 66 LD DATA_FLASH
0xa0, // 67 LD MSB 0
0xba, // 68 LD LSB 10
0x90, // 69 LD DR_PARALLEL
0xbb, // 6a LD LSB 11
0x90, // 6b LD DR_PARALLEL
0xb9, // 6c LD LSB 9
0x90, // 6d LD DR_PARALLEL
0xbb, // 6e LD LSB 11
0x90, // 6f LD DR_PARALLEL
0xba, // 70 LD LSB 10
0x90, // 71 LD DR_PARALLEL
//---------------------------
// read_status & check_status
//---------------------------
//wait_card_ready
//---------------
//init_timeout
//------------
0xb0, // 72 LD LSB 00
0x85, // 73 LD ADR_BUFFER01
0x84, // 74 LD ADR_BUFFER00
0x88, // 75 LD CMP00
0xaf, // 76 LD MSB 15
0x89, // 77 LD CMP01
// :wait_card_ready
//---------------
0x27, // 78 ADDER16 ADR_BUFFER0
0xd, // 79 CP ADR_BUFFER0<CMP0
// JP :no_timeout
0x42, // 7a JP 2
0x7, // 7b STATUS STOP ERROR // timeout 20ms
// :no_timeout
//----------
0xd0, // 7c LD A DR_PARALLEL
0x33, // 7d EXCHANGE
0x28, // 7e BCLR1 //test R/B
// JP :wait_card_ready
0x67, // 7f JP -7
// :read_status_command_latch_cycle
//-------------------------------
0xa7, // 80 LD MSB 7
0xb0, // 81 LD LSB 0
0x8c, // 82 LD DATA_FLASH
0xa0, // 83 LD MSB 0
0xba, // 84 LD LSB 10
0x90, // 85 LD DR_PARALLEL
0xbb, // 86 LD LSB 11
0x90, // 87 LD DR_PARALLEL
0xb9, // 88 LD LSB 9
0x90, // 89 LD DR_PARALLEL
0xbb, // 8a LD LSB 11
0x90, // 8b LD DR_PARALLEL
0xba, // 8c LD LSB 10
0x90, // 8d LD DR_PARALLEL
// :init_read_status_seq
//---------------------
0xa0, // 8e LD MSB 0
0xb9, // 8f LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 90 LD CTRL_FCI // PARALLEL Port driven by FCI
// :read_status_seq
//----------------
0xa0, // 91 LD MSB 0
0xb2, // 92 LD LSB 2
0x90, // 93 LD DR_PARALLEL
0x0, // 94 NOP
0xcc, // 95 LD A DATA_FLASH // load DATA_FLASH
// : check_status
//-------------
0x33, // 96 EXCHANGE
0x2a, // 97 BCLR3
//JP :error_status
0x2b, // 98 BCLR4
//JP :error_status
//CP A<X
//JP :no_error
//:error_status
//------------
//STATUS STOP
// :no_error
//--------
0xa0, // 99 LD MSB 0
0xba, // 9a LD LSB 10
0x90, // 9b LD DR_PARALLEL
//------------
//end_of_block
//------------
//inc_addr
//--------
0xb0, // 9c LD LSB 0
0xa0, // 9d LD MSB 0
0x85, // 9e LD ADR_BUFFER01 // buffer 0 address ( 8..15 )
0xae, // 9f LD MSB 14
0xb3, // a0 LD LSB 03
0x84, // a1 LD ADR_BUFFER00 // buffer 0 address ( 0..7 )
0xdb, // a2 LD A DATA_BUFFER0
0x2, // a3 CLC
0x25, // a4 ADDER8 X
0x9b, // a5 LD DATA_BUFFER0
0xbf, // a6 LD LSB 15
0xaf, // a7 LD MSB 15
0x84, // a8 LD ADR_BUFFER00 // buffer 0 address ( 7..0 )
0xdb, // a9 LD A DATA_BUFFER0
0x2, // aa CLC
0x24, // ab SUB8 X
0x9b, // ac LD DATA_BUFFER0
0x8, // ad CP A=>X
// JP :process_continue
0x42, // ae JP 2
0x5, // af STATUS STOP // end of process
// :process_continue
0xa1, // b0 LD MSB 1
0xb4, // b1 LD LSB 4
0xb, // b2 CP ALWAYS
0x60, // b3 BRANCH⌨️ 快捷键说明
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