📄 smc_dtc_mapzone_end.hex
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// *****************************************************************
// * NOTICE: The information contained in this file is proprietary *
// * to SGS-THOMSON Microelectronics and is being made available *
// * to ST customers under strict non-disclosure agreements. *
// * Use or disclosure of this information is permissible only *
// * under the terms of the existing non-disclosure agreement. *
// *****************************************************************
// Written by Christophe BRICOUT
// Created by MPmanCompiler.exe (v3.0) Mon Apr 15 16:47:10 2002
//===================================================================
//
// SMART MEDIA CARD
//
//===================================================================
//----------------
// SMC_DTC_MapZone
//----------------
// :init_command_address
//------------------------------------------------------------------------
// START ADDRESS FOR make the map zone
// INPUT:
// 0xE2-0xE5 is the address of the 1st cluster to be scanned
// 0xE6: = 3 for 3 bytes address// = 4 for 4 bytes address
// 0xD0-0xD1 is the start address of the lookup table
// 0xD2-0xD3 is the end address of the loopup table
//------------------------------------------------------------------------
0xa0, // 0 LD MSB 0
0xbf, // 1 LD LSB 15
0x91, // 2 LD DDR_PARALLEL
0x92, // 3 LD OR_PARALLEL
0xaf, // 4 LD MSB 15
0x83, // 5 LD MASK
0x31, // 6 XOR
0x9f, // 7 LD BUFFER_MNGT // Clear segment offset
0x85, // 8 LD ADR_BUFFER01
0x86, // 9 LD ADR_BUFFER10
0x8a, // a LD CMP10
0xb1, // b LD LSB 1
0x87, // c LD ADR_BUFFER11 // buffer pointer 1 = 0x0100
0xb5, // d LD LSB 5
0x8b, // e LD CMP11 // CMP1 = 0x0500
//-------------------------
// Output the command 0x50
//-------------------------
// :start_read_spare_area
0xa1, // f LD MSB 1 //data_flash port = output
0xb9, // 10 LD LSB 9 //DATA_FLASH Port driven by FCI
0x8d, // 11 LD CTRL_FCI //PARALLEL Port driven by FCI
// :pre_wait_card_ready
//---------------
0xd0, // 12 LD A DR_PARALLEL
0x33, // 13 EXCHANGE
0x28, // 14 BCLR1 // test busy line
// JP :pre_wait_card_ready
0x63, // 15 JP -3
0xa5, // 16 LD MSB 5
0xb0, // 17 LD LSB 0
0x8c, // 18 LD DATA_FLASH // command Read(3)
0xba, // 19 LD LSB 10
0x90, // 1a LD DR_PARALLEL // WE = 1, CLE = 0
0xbb, // 1b LD LSB 11
0x90, // 1c LD DR_PARALLEL // WE = 1, CLE = 1
0xb9, // 1d LD LSB 9
0x90, // 1e LD DR_PARALLEL // WE = 0, CLE = 1
0xbb, // 1f LD LSB 11
0x90, // 20 LD DR_PARALLEL // WE = 1, CLE = 1
0xba, // 21 LD LSB 10
0x90, // 22 LD DR_PARALLEL // WE = 1, CLE = 0
//------------------------------------
// Output the 3 or 4 bytes of address
//------------------------------------
0xa0, // 23 LD MSB 0
0xb1, // 24 LD LSB 1
0x81, // 25 LD X // X = 1
0xae, // 26 LD MSB 14
0xb6, // 27 LD LSB 6
0x84, // 28 LD ADR_BUFFER00 // buffer pointer 0 = 0x00E6
0xdb, // 29 LD A DATA_BUFFER0 // load the number of address bytes
0x82, // 2a LD Y
0x3c, // 2b DECY
0xc5, // 2c LD A ADR_BUFFER01 // A = 0
// :loop_send_address
//-----------------
0x26, // 2d SUB16 ADR_BUFFER0 // send address from high byte to low byte
0x8c, // 2e LD DATA_FLASH
0xa0, // 2f LD MSB 0
0xbe, // 30 LD LSB 14
0x90, // 31 LD DR_PARALLEL // ALE = 1, WE = 1
0xbc, // 32 LD LSB 12
0x90, // 33 LD DR_PARALLEL // ALE = 1, WE = 0
0xbe, // 34 LD LSB 14
0x90, // 35 LD DR_PARALLEL // ALE = 1, WE = 1
0xdb, // 36 LD A DATA_BUFFER0
0x3c, // 37 DECY
// JP :loop_send_address
0x6b, // 38 JP -11
0xa0, // 39 LD MSB 0
0xba, // 3a LD LSB 10
0x90, // 3b LD DR_PARALLEL // ALE = 0, WE = 1
//LD MSB 0 // data_flash port = intput
0xb9, // 3c LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 3d LD CTRL_FCI // PARALLEL Port driven by FCI
//---------------------
// Read the spare area
//---------------------
// :init_read_spare
0xb2, // 3e LD LSB 2
0x88, // 3f LD CMP00 // CMP00 = 0x02 for toggling RD line
0xbf, // 40 LD LSB 15
0x82, // 41 LD Y // Y = 15
0xae, // 42 LD MSB 14
0xb7, // 43 LD LSB 07
0x84, // 44 LD ADR_BUFFER00 // ADR0 = 0x00E7, points to spare area
0x89, // 45 LD CMP01 // save this address for later use
// :wait_card_ready
//---------------
0xd0, // 46 LD A DR_PARALLEL
0x33, // 47 EXCHANGE
0x28, // 48 BCLR1 // test busy line
// JP :wait_card_ready
0x63, // 49 JP -3
// read_spare
//------------
// :read_spare
0xc8, // 4a LD A CMP00
0x90, // 4b LD DR_PARALLEL // RD = 0
0xba, // 4c LD LSB 10
0x90, // 4d LD DR_PARALLEL // RD = 1
0xcc, // 4e LD A DATA_FLASH // load DATA_FLASH
0x9b, // 4f LD DATA_BUFFER0
0x27, // 50 ADDER16 ADR_BUFFER0
0x3c, // 51 DECY
// JP :read_spare
0x68, // 52 JP -8
//-------------------------------
// Check the spare area is valid
//-------------------------------
0xc9, // 53 LD A CMP01
0x82, // 54 LD Y // Y = 0x00E7, points to spare area
0xc0, // 55 LD A <Y> // load 1st byte of reserved area
0x31, // 56 XOR
0x8, // 57 CP A=>X // X = 1
// JP :spare_area_check_FF
0x59, // 58 JP 25
0x3d, // 59 INCY
0xc0, // 5a LD A <Y> // load 2nd byte of reserved area
0x31, // 5b XOR
0x8, // 5c CP A=>X
// JP :spare_area_check_FF
0x54, // 5d JP 20
0x3d, // 5e INCY
0xc0, // 5f LD A <Y> // load 3rd byte of reserved area
0x31, // 60 XOR
0x8, // 61 CP A=>X
// JP :spare_area_check_FF
0x4f, // 62 JP 15
0x3d, // 63 INCY
0xc0, // 64 LD A <Y> // load 4th byte of reserved area
0x31, // 65 XOR
0x8, // 66 CP A=>X
// JP :spare_area_check_FF
0x4a, // 67 JP 10
0x3d, // 68 INCY
0xc0, // 69 LD A <Y> // load data status byte
0x31, // 6a XOR
0x8, // 6b CP A=>X
// JP :spare_area_check_FF
0x45, // 6c JP 5
0x3d, // 6d INCY
0xc0, // 6e LD A <Y> // load block status byte
0x3d, // 6f INCY
0x31, // 70 XOR
// :spare_area_check_FF
//-----------------
0x1, // 71 SEC
0x8, // 72 CP A=>X
// JP :spare_area_address_error
0x5a, // 73 JP 26
0xc0, // 74 LD A <Y> // load high byte of block address 1
0x85, // 75 LD ADR_BUFFER01
0x3d, // 76 INCY
0xc0, // 77 LD A <Y> // load low byte of block address 1
0x84, // 78 LD ADR_BUFFER00
0x81, // 79 LD X // X = low byte of block address 1
0x3d, // 7a INCY
0x3d, // 7b INCY // skip 1st byte of ECC2
0x3d, // 7c INCY // skip 2nd byte of ECC2
0x3d, // 7d INCY // skip 3rd byte of ECC2
0xc0, // 7e LD A <Y> // load high byte of block address 2
0x89, // 7f LD CMP01
0x3d, // 80 INCY
0xc0, // 81 LD A <Y> // load low byte of block address 2
0x88, // 82 LD CMP00
0xd, // 83 CP ADR_BUFFER0<CMP0
// JP :spare_area_error
0x52, // 84 JP 18
0x2, // 85 CLC
0x24, // 86 SUB8 X // CMP00 - ADR_BUFFER00
0xa, // 87 CP CARRY
// JP :spare_area_error
0x4e, // 88 JP 14
0xc5, // 89 LD A ADR_BUFFER01
0x81, // 8a LD X
0xc9, // 8b LD A CMP01
0x24, // 8c SUB8 X
// :spare_area_address_error
//------------------------
0xa, // 8d CP CARRY
// JP :spare_area_error
0x48, // 8e JP 8
//---------------------
// check the parity bit
//---------------------
0x1, // 8f SEC
0xc4, // 90 LD A ADR_BUFFER00
0x31, // 91 XOR
0xc5, // 92 LD A ADR_BUFFER01
0x31, // 93 XOR
0xa, // 94 CP CARRY
// JP :got_a_good_address
0x53, // 95 JP 19
// :spare_area_error
//----------------
0xa0, // 96 LD MSB 0
0xb1, // 97 LD LSB 1
0x81, // 98 LD X // X = 1
0x33, // 99 EXCHANGE // A = 0x10
0x9c, // 9a LD DATA_BUFFER1
0x2f, // 9b ADDER16 ADR_BUFFER1
0xa0, // 9c LD MSB 0
0x9c, // 9d LD DATA_BUFFER1 // save as 0x1000, this is an invalid cluster
0x2f, // 9e ADDER16 ADR_BUFFER1
0xb, // 9f CP ALWAYS
// JP :increase_cluster_address
0x5a, // a0 JP 26
// :got_logical_address
//-------------------
0xc5, // a1 LD A ADR_BUFFER01 // high byte of the address
0x33, // a2 EXCHANGE
0x28, // a3 BCLR1 // bit12 of the address must be 1
// JP :spare_area_error
0x6e, // a4 JP -14
0x33, // a5 EXCHANGE
0xb, // a6 CP ALWAYS
// JP :save_logical_address
0x4d, // a7 JP 13
// :got_a_good_address
//------------------
0xa0, // a8 LD MSB 0
0xb1, // a9 LD LSB 1
0x81, // aa LD X // X = 0x01
0xc4, // ab LD A ADR_BUFFER00
0x31, // ac XOR
0x8, // ad CP A=>X
// JP :got_logical_address
0x6d, // ae JP -13
0xc5, // af LD A ADR_BUFFER01
0x31, // b0 XOR
0x8, // b1 CP A=>X
// JP :got_logical_address
0x71, // b2 JP -17
// :got_free_cluster
//----------------
//*LD MSB 14
//*LD LSB 7 // A = 0xE7, will be 0x73 after shift right
0xc3, // b3 LD A MASK
// :save_logical_address
//--------------------
0x9c, // b4 LD DATA_BUFFER1 // save the high byte of the address
0x2f, // b5 ADDER16 ADR_BUFFER1
0xc4, // b6 LD A ADR_BUFFER00
0x28, // b7 BCLR1 // clear the parity bit
0x9c, // b8 LD DATA_BUFFER1 // save the low byte of the address
0x2f, // b9 ADDER16 ADR_BUFFER1
// :increase_cluster_address
//------------------------
0xc3, // ba LD A MASK
0x84, // bb LD ADR_BUFFER00
0x31, // bc XOR
0x85, // bd LD ADR_BUFFER01 // ADR0 = 0x00FF, points to cluster size
0xdb, // be LD A DATA_BUFFER0
0x81, // bf LD X // X = the size of the cluster
0x2, // c0 CLC
0xae, // c1 LD MSB 14
0xb5, // c2 LD LSB 5
0x82, // c3 LD Y // Y = 0xE5, points to the cluster address
0xc0, // c4 LD A <Y>
0x25, // c5 ADDER8 X
0x80, // c6 LD <Y> // byte 0 of the address
0x3c, // c7 DECY // Y = 0xE4
0xc5, // c8 LD A ADR_BUFFER01
0x81, // c9 LD X // clear X
0xc0, // ca LD A <Y>
0x25, // cb ADDER8 X // byte 1 of the address
0x80, // cc LD <Y>
0x3c, // cd DECY // Y = 0xE3
0xc0, // ce LD A <Y>
0x25, // cf ADDER8 X
0x80, // d0 LD <Y> // byte 2 of the address
// :check_next_cluster
//------------------
0xa0, // d1 LD MSB 0
0xbf, // d2 LD LSB 12
0xf, // d3 CP ADR_BUFFER1<CMP1
0x60, // d4 BRANCH :start_read_spare_area
// :no_more_clusters
0x0, // d5 NOP
0x0, // d6 NOP
0x0, // d7 NOP
0x5, // d8 STATUS STOP
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