📄 smc_dtc_markpages256_end.hex
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// *****************************************************************
// * NOTICE: The information contained in this file is proprietary *
// * to SGS-THOMSON Microelectronics and is being made available *
// * to ST customers under strict non-disclosure agreements. *
// * Use or disclosure of this information is permissible only *
// * under the terms of the existing non-disclosure agreement. *
// *****************************************************************
// Written by Christophe BRICOUT
// Created by MPmanCompiler.exe (v3.0) Tue Mar 25 23:27:13 2003
//===================================================================
//
// SMART MEDIA CARD
//
//===================================================================
//----------------------
// dtc_smc_mark_page.fsm
//----------------------
//--------------------------
//init_write_number_of_block
//--------------------------
0xa0, // 0 LD MSB 0
0xb1, // 1 LD LSB 1
0x81, // 2 LD X // X<=1
//-----------------
//init_dtc_ctrl_reg
//-----------------
0xa1, // 3 LD MSB 1 // data_flash port = output
0xb9, // 4 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 5 LD CTRL_FCI // PARALLEL Port driven by FCI
//-------------------------------
//command_latch_cycle (Read2 CMD)
//-------------------------------
//LD MSB 5
//LD LSB 0
//LD DATA_FLASH
//for 256mb
//----------
0xa0, // 6 LD MSB 0
0xb0, // 7 LD LSB 0
0x85, // 8 LD ADR_BUFFER01
0x9f, // 9 LD BUFFER_MNGT
0xad, // a LD MSB 13
0x84, // b LD ADR_BUFFER00
//LD MSB 8 //send first write command from 0xd0
//LD LSB 0
0xdb, // c LD A DATA_BUFFER0
0x8c, // d LD DATA_FLASH
0xa0, // e LD MSB 0
0xba, // f LD LSB 10
0x90, // 10 LD DR_PARALLEL
0xbb, // 11 LD LSB 11
0x90, // 12 LD DR_PARALLEL
0xb9, // 13 LD LSB 9
0x90, // 14 LD DR_PARALLEL
0xbb, // 15 LD LSB 11
0x90, // 16 LD DR_PARALLEL
0xba, // 17 LD LSB 10
0x90, // 18 LD DR_PARALLEL
//for 256mb
//----------
0xac, // 19 LD MSB 12 //Set a Flag at 0xc0= 0x00 for the card with 2K page
0xb0, // 1a LD LSB 0
0x82, // 1b LD Y
0xc0, // 1c LD A <Y>
0x28, // 1d BCLR1 //if 256mb no second cmd is required
// LD Y
// DECY
// JP :send_address
0x51, // 1e JP 17
//send 0x80 cmd for other FLash
// :process_continue1
//------------------
0xa1, // 1f LD MSB 1 // data_flash port = output
0xb9, // 20 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 21 LD CTRL_FCI // PARALLEL Port driven by FCI
0xa8, // 22 LD MSB 8
0xb0, // 23 LD LSB 0
0x8c, // 24 LD DATA_FLASH
// :send_nxt_cmd
//-------------
0xba, // 25 LD LSB 10
0x90, // 26 LD DR_PARALLEL // WE = 1, CLE = 0
0xbb, // 27 LD LSB 11
0x90, // 28 LD DR_PARALLEL // WE = 1, CLE = 1
0xb9, // 29 LD LSB 9
0x90, // 2a LD DR_PARALLEL // WE = 0, CLE = 1
0xbb, // 2b LD LSB 11
0x90, // 2c LD DR_PARALLEL // WE = 1, CLE = 1
0xba, // 2d LD LSB 10
0x90, // 2e LD DR_PARALLEL // WE = 1, CLE = 0
//-----------------
//init_dtc_ctrl_reg
//-----------------
//LD MSB 1 // data_flash port = output
//LD LSB 9 // DATA_FLASH Port driven by FCI
//LD CTRL_FCI // PARALLEL Port driven by FCI
// :send_address
0xa0, // 2f LD MSB 0
0xb0, // 30 LD LSB 0
0x85, // 31 LD ADR_BUFFER01
0xae, // 32 LD MSB 14
0xb6, // 33 LD LSB 06
0x84, // 34 LD ADR_BUFFER00 // buffer pointer 0 = 0x00E6
0xdb, // 35 LD A DATA_BUFFER0
0x82, // 36 LD Y // Y = number of address bytes
0x3c, // 37 DECY
0xbc, // 38 LD LSB 12
0x89, // 39 LD CMP01 // CMP01 = 12, for send address toggling lines
0xbe, // 3a LD LSB 14
0x90, // 3b LD DR_PARALLEL // ALE = 1, WE = 1
// LD A ADR_BUFFER01 // clear A as the first byte, it is always 0,for 256mb
// LD ADR_BUFFER10 // clear low byte of ADR1
// LD CMP10 // clear low byte of CMP1
// LD BUFFER_MNGT // clear SEGment offset for using Y on ECC check
0x26, // 3c SUB16 ADR_BUFFER0 // send address from high byte to low byte
// :loop_send_address
//-----------------
// SUB16 ADR_BUFFER0 // send address from high byte to low byte
0xdb, // 3d LD A DATA_BUFFER0
0x8c, // 3e LD DATA_FLASH // Output the address bytes
0xc9, // 3f LD A CMP01
0x90, // 40 LD DR_PARALLEL // ALE = 1, WE = 0
0xbe, // 41 LD LSB 14
0x90, // 42 LD DR_PARALLEL // ALE = 1, WE = 1
0x26, // 43 SUB16 ADR_BUFFER0 // send address from high byte to low byte
// LD A DATA_BUFFER0
0x3c, // 44 DECY
// JP :loop_send_address
0x68, // 45 JP -8
0xa0, // 46 LD MSB 0
0xba, // 47 LD LSB 10
0x90, // 48 LD DR_PARALLEL // ALE = 0, WE = 1
//---------------------
//wait_sdi_addr_ready
//---------------------
// :init_timeout
//------------
//LD LSB 00
//LD ADR_BUFFER01 // buffer 0 address ( 8..15 )
//LD ADR_BUFFER00 // buffer 0 address ( 0..7 )
//LD CMP00
//LD MSB 15
//LD CMP01
// :wait_sdi_addr_ready
//---------------------
//ADDER16 ADR_BUFFER0
//CP ADR_BUFFER0<CMP0
//JP :sdi_addr_no_timeout
//STATUS STOP ERROR // timeout >20ms
// :sdi_addr_no_timeout
//---------------------
//LD A DR_PARALLEL
//EXCHANGE
//BCLR1 //test R/B
//JP :wait_sdi_addr_ready
//------------
// write_spare
//------------
//init_write_spare
//----------------
0xa0, // 49 LD MSB 0
0xb0, // 4a LD LSB 0
0x85, // 4b LD ADR_BUFFER01 // buffer 0 address ( 15..8 )
0x89, // 4c LD CMP01
0xae, // 4d LD MSB 14
0xb7, // 4e LD LSB 07
0x84, // 4f LD ADR_BUFFER00
0xaf, // 50 LD MSB 15
0x88, // 51 LD CMP00
// :write_spare
//-----------
0xdb, // 52 LD A DATA_BUFFER0
0x8c, // 53 LD DATA_FLASH
0xa0, // 54 LD MSB 0
0xb8, // 55 LD LSB 8
0x90, // 56 LD DR_PARALLEL
0xba, // 57 LD LSB 10
0x90, // 58 LD DR_PARALLEL
0x27, // 59 ADDER16 ADR_BUFFER0
0xd, // 5a CP ADR_BUFFER0<CMP0
// JP :write_spare
0x69, // 5b JP -9
0xaf, // 5c LD MSB 15
0xbf, // 5d LD LSB 15
0x84, // 5e LD ADR_BUFFER00 //point to 0xff
0xdb, // 5f LD A DATA_BUFFER0
0x2, // 60 CLC
0x24, // 61 SUB8 X
0x9b, // 62 LD DATA_BUFFER0
0x9, // 63 CP A<X //changed for bug
0xa9, // 64 LD MSB 9
0xbf, // 65 LD LSB 15
0x60, // 66 BRANCH :program_page
0xac, // 67 LD MSB 12
0xb0, // 68 LD LSB 0
0x84, // 69 LD ADR_BUFFER00
0xdb, // 6a LD A DATA_BUFFER0
0x38, // 6b BSET1
// JP :program_page
0xa9, // 6c LD MSB 9
0xbf, // 6d LD LSB 15
// :program_page1
0x60, // 6e BRANCH :program_page
0xae, // 6f LD MSB 14
0xb4, // 70 LD LSB 4
0x84, // 71 LD ADR_BUFFER00
0xa0, // 72 LD MSB 0
0xb2, // 73 LD LSB 2
0x82, // 74 LD Y
0xdb, // 75 LD A DATA_BUFFER0
0x2, // 76 CLC
0x2d, // 77 ADDER8 Y
0x9b, // 78 LD DATA_BUFFER0
0xa1, // 79 LD MSB 1
0xb0, // 7a LD LSB 0
0x82, // 7b LD Y
// LD MSB 14
// LD LSB 5
0x27, // 7c ADDER16 ADR_BUFFER0
// LD ADR_BUFFER00
0xdb, // 7d LD A DATA_BUFFER0
0x2, // 7e CLC
0x2d, // 7f ADDER8 Y
0x9b, // 80 LD DATA_BUFFER0
0x33, // 81 EXCHANGE
0x3a, // 82 BSET3
// JP :next_page
0x4e, // 83 JP 14
0xae, // 84 LD MSB 14
0xb6, // 85 LD LSB 6
0x84, // 86 LD ADR_BUFFER00
// LD MSB 13
// LD LSB 2 //reload address bytes into 0xd2
// LD Y
// LD A DATA_BUFFER0
// LD <Y>
0xa0, // 87 LD MSB 0
0xb2, // 88 LD LSB 2
0x9b, // 89 LD DATA_BUFFER0 //load 2 in 0xe6 to change number of add bytes
//send 0x85 command for random data output
//----------------------------------------
0xa8, // 8a LD MSB 8
0xb5, // 8b LD LSB 5
0x8c, // 8c LD DATA_FLASH
0xa2, // 8d LD MSB 2
0xb5, // 8e LD LSB 5
0xb, // 8f CP ALWAYS
0x60, // 90 BRANCH :send_nxt_cmd
// LD MSB 6
// LD LSB 9
// BRANCH :write_next_col
// :next_page
0xad, // 91 LD MSB 13
0xb2, // 92 LD LSB 2
0x82, // 93 LD Y
0xae, // 94 LD MSB 14
0xb6, // 95 LD LSB 6
0x84, // 96 LD ADR_BUFFER00
0xc0, // 97 LD A <Y>
0x9b, // 98 LD DATA_BUFFER0 //reload again the number of address bytes
// LD MSB 14
// LD LSB 5
0x26, // 99 SUB16 ADR_BUFFER0
0xc5, // 9a LD A ADR_BUFFER01
0x9b, // 9b LD DATA_BUFFER0
0x26, // 9c SUB16 ADR_BUFFER0
0xb2, // 9d LD LSB 2
0x9b, // 9e LD DATA_BUFFER0
//----------------------------
// :Page_Pgm_command_latch_cycle
//----------------------------
// :program_page
//-------------
0xa1, // 9f LD MSB 1
0xb0, // a0 LD LSB 0
0x8c, // a1 LD DATA_FLASH
0xa0, // a2 LD MSB 0
0xba, // a3 LD LSB 10
0x90, // a4 LD DR_PARALLEL
0xbb, // a5 LD LSB 11
0x90, // a6 LD DR_PARALLEL
0xb9, // a7 LD LSB 9
0x90, // a8 LD DR_PARALLEL
0xbb, // a9 LD LSB 11
0x90, // aa LD DR_PARALLEL
0xba, // ab LD LSB 10
0x90, // ac LD DR_PARALLEL
//---------------------------
// read_status & check_status
//---------------------------
//wait_card_ready
//---------------
//init_timeout
//------------
0xb0, // ad LD LSB 00
0x85, // ae LD ADR_BUFFER01
0x84, // af LD ADR_BUFFER00
0x88, // b0 LD CMP00
0xaf, // b1 LD MSB 15
0x89, // b2 LD CMP01
// :wait_card_ready
//---------------
0x27, // b3 ADDER16 ADR_BUFFER0
0xd, // b4 CP ADR_BUFFER0<CMP0
// JP :no_timeout
0x42, // b5 JP 2
0x7, // b6 STATUS STOP ERROR // timeout 20ms
// :no_timeout
//----------
0xd0, // b7 LD A DR_PARALLEL
0x33, // b8 EXCHANGE
0x28, // b9 BCLR1 //test R/B
// JP :wait_card_ready
0x67, // ba JP -7
// :read_status_command_latch_cycle
//-------------------------------
0xa7, // bb LD MSB 7
0xb0, // bc LD LSB 0
0x8c, // bd LD DATA_FLASH
0xa0, // be LD MSB 0
0xba, // bf LD LSB 10
0x90, // c0 LD DR_PARALLEL
0xbb, // c1 LD LSB 11
0x90, // c2 LD DR_PARALLEL
0xb9, // c3 LD LSB 9
0x90, // c4 LD DR_PARALLEL
0xbb, // c5 LD LSB 11
0x90, // c6 LD DR_PARALLEL
0xba, // c7 LD LSB 10
0x90, // c8 LD DR_PARALLEL
// :init_read_status_seq
//---------------------
0xa0, // c9 LD MSB 0
0xb9, // ca LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // cb LD CTRL_FCI // PARALLEL Port driven by FCI
// :read_status_seq
//----------------
0xa0, // cc LD MSB 0
0xb2, // cd LD LSB 2
0x90, // ce LD DR_PARALLEL
0x0, // cf NOP
0xcc, // d0 LD A DATA_FLASH // load DATA_FLASH
// : check_status
//-------------
//EXCHANGE
//BCLR3
//JP :error_status
//BCLR4
//JP :error_status
//CP A<X
0x28, // d1 BCLR1
// JP :no_error
0x42, // d2 JP 2
// :error_status
//------------
0x5, // d3 STATUS STOP
// :no_error
//--------
0xa0, // d4 LD MSB 0
0xba, // d5 LD LSB 10
0x90, // d6 LD DR_PARALLEL
//------------
//end_of_block
//------------
//inc_addr
//--------
//for 256mb
0xb0, // d7 LD LSB 0
0xa0, // d8 LD MSB 0
0x85, // d9 LD ADR_BUFFER01 // buffer 0 address ( 8..15 )
0xaf, // da LD MSB 15
0xbf, // db LD LSB 15
0x84, // dc LD ADR_BUFFER00
0xdb, // dd LD A DATA_BUFFER0
0x8, // de CP A=>X
// JP :inc_page_addr
0x42, // df JP 2
0x5, // e0 STATUS STOP
// :inc_page_addr
//-------------
0xac, // e1 LD MSB 12
0xb0, // e2 LD LSB 0
0x84, // e3 LD ADR_BUFFER00
0xdb, // e4 LD A DATA_BUFFER0
0x38, // e5 BSET1
// JP :512bytes_page
0x46, // e6 JP 6
0xae, // e7 LD MSB 14
0xb3, // e8 LD LSB 03
0x84, // e9 LD ADR_BUFFER00 // buffer 0 address ( 0..7 )
0xb, // ea CP ALWAYS
// JP :process_continue
0x44, // eb JP 4
// :512bytes_page
//-------------
0xae, // ec LD MSB 14
0xb4, // ed LD LSB 04
0x84, // ee LD ADR_BUFFER00
// :process_continue
//-----------------
0xdb, // ef LD A DATA_BUFFER0
0x2, // f0 CLC
0x25, // f1 ADDER8 X
0x9b, // f2 LD DATA_BUFFER0
0xa1, // f3 LD MSB 1
0xbf, // f4 LD LSB 15
//LD Y
//LD A <Y>
0xb, // f5 CP ALWAYS
0x60, // f6 BRANCH⌨️ 快捷键说明
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