smc_dtc_play_end.hex
来自「HID-Ukey底层源码实现（st72651芯片） windows上层驱动」· HEX 代码 · 共 455 行
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// *****************************************************************
// * NOTICE: The information contained in this file is proprietary *
// * to SGS-THOMSON Microelectronics and is being made available *
// * to ST customers under strict non-disclosure agreements. *
// * Use or disclosure of this information is permissible only *
// * under the terms of the existing non-disclosure agreement. *
// *****************************************************************
// Written by Christophe BRICOUT
// Created by MPmanCompiler.exe (v3.0) Fri Apr 06 15:43:32 2001
//===================================================================
//
// SMART MEDIA CARD
//
//===================================================================
//-------------
// smc_dtc_play
//-------------
//------------------------------------------------------------------
// START ADDRESS FOR read data to Buffer_0
//------------------------------------------------------------------
// :read_buffer_0
0xb1, // 0 LD LSB 1
0xb, // 1 CP ALWAYS
// JP :init_read_command
0x42, // 2 JP 2
//------------------------------------------------------------------
// START ADDRESS FOR read data to Buffer_1
//------------------------------------------------------------------
// :read_buffer_1
0xb3, // 3 LD LSB 3
// :init_read_command
0xa0, // 4 LD MSB 0
0x87, // 5 LD ADR_BUFFER11
//LD MSB 0 // data_flash port = intput
0xb9, // 6 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 7 LD CTRL_FCI // PARALLEL Port driven by FCI
0xa2, // 8 LD MSB 2 // ECC Mode & Reset TMP Reg
0x8d, // 9 LD CTRL_FCI // PARALLEL Port driven by FCI
// :init_read_page
//--------------
0xc5, // a LD A ADR_BUFFER01 // It must be zero
0x86, // b LD ADR_BUFFER10 // clear low byte of pointer 1 for reading
0x89, // c LD CMP01
0xb2, // d LD LSB 2
0x88, // e LD CMP00 // CMP0 = 0x0002, will use for RD toggling
0x84, // f LD ADR_BUFFER00 // buffer pointer 0 = 0x0002
// :wait_read_ready
//---------------
0x27, // 10 ADDER16 ADR_BUFFER0
0xc, // 11 CP ADR_BUFFER0=>CMP0
// JP :test_busy_line
0x43, // 12 JP 3
0x0, // 13 NOP // the waiting loop is timeout
0x7, // 14 STATUS STOP ERROR // return with error
// :test_busy_line
//--------------
0xd0, // 15 LD A DR_PARALLEL
0x33, // 16 EXCHANGE
0x28, // 17 BCLR1
// JP :wait_read_ready
0x68, // 18 JP -8
0xc6, // 19 LD A ADR_BUFFER10
0x85, // 1a LD ADR_BUFFER01 // clear high byte of pointer 0
0x82, // 1b LD Y // clear Y, Y = 256
0xaf, // 1c LD MSB 15
0xb8, // 1d LD LSB 8
0x84, // 1e LD ADR_BUFFER00 // buffer pointer 0 = 0x00F8, points the ECC memory
// :read_256_bytes
//--------------
// :read_dat_sec
//-------------
0xc8, // 1f LD A CMP00
0x90, // 20 LD DR_PARALLEL // RD = 0
0xba, // 21 LD LSB 10
0x90, // 22 LD DR_PARALLEL // RD = 1
0xcc, // 23 LD A DATA_FLASH // load DATA_FLASH
0x9c, // 24 LD DATA_BUFFER1
0x9d, // 25 LD ECC_CRC // load ECC_CRC REG
0x2, // 26 CLC // Clear carry
0x31, // 27 XOR // Update carry
0xdd, // 28 LD A ECC_CRC // AUTO UPDATE OF Line PARITY 1
0xdd, // 29 LD A ECC_CRC // AUTO UPDATE OF Line PARITY 2
0xdd, // 2a LD A ECC_CRC // AUTO UPDATE OF column PARITY
0x2f, // 2b ADDER16 ADR_BUFFER1
0x3d, // 2c INCY
// JP :read_dat_sec
0x6e, // 2d JP -14
//-------------------
// routine ecc_calcul
//-------------------
// :read_ecc_calcul
0xde, // 2e LD A TMP_ECC // first read (Line parity 1)
0x9b, // 2f LD DATA_BUFFER0
0xdd, // 30 LD A ECC_CRC // -- INCR CRC_ECC_STATE --
0x27, // 31 ADDER16 ADR_BUFFER0
0xde, // 32 LD A TMP_ECC // second read (Line parity 2)
0x9b, // 33 LD DATA_BUFFER0
0xdd, // 34 LD A ECC_CRC // -- INCR CRC_ECC_STATE --
0x27, // 35 ADDER16 ADR_BUFFER0
0xde, // 36 LD A TMP_ECC // third read ( column parity)
0x9b, // 37 LD DATA_BUFFER0
0x27, // 38 ADDER16 ADR_BUFFER0
0xc7, // 39 LD A ADR_BUFFER11
0x28, // 3a BCLR1
// JP :read_dat_sec
0x7c, // 3b JP -28
//------------------------------
// START ADDRESS FOR read_spare
//------------------------------
// :init_read_spare
0xbf, // 3c LD LSB 15
0x82, // 3d LD Y // Y = 15
0xae, // 3e LD MSB 14
0xb6, // 3f LD LSB 06
0x84, // 40 LD ADR_BUFFER00 // buffer pointer0 = 0x00E6,
// read_spare
//-----------
// :read_spare
0x27, // 41 ADDER16 ADR_BUFFER0
0xc8, // 42 LD A CMP00
0x90, // 43 LD DR_PARALLEL // RD = 0
0xba, // 44 LD LSB 10
0x90, // 45 LD DR_PARALLEL // RD = 1
0xcc, // 46 LD A DATA_FLASH // load DATA_FLASH
0x9b, // 47 LD DATA_BUFFER0
0x3c, // 48 DECY
// JP :read_spare
0x68, // 49 JP -8
0x5, // 4a STATUS STOP
//------------------------------------------------------------------
//------------------------------------------------------------------
//------------------------------------------------------------------
// START ADDRESS FOR write data from Buffer_0
//------------------------------------------------------------------
// :write_buffer_0
0xb1, // 4b LD LSB 1
0xb, // 4c CP ALWAYS
// JP :init_write_command
0x42, // 4d JP 2
//------------------------------------------------------------------
// START ADDRESS FOR write data from Buffer_1
//------------------------------------------------------------------
// :write_buffer_1
0xb3, // 4e LD LSB 3
// :init_write_command
0xa0, // 4f LD MSB 0
0x87, // 50 LD ADR_BUFFER11
0xb8, // 51 LD LSB 8
0x88, // 52 LD CMP00 // CMP00 = 0x08, will be used for toggling WE line
0xb0, // 53 LD LSB 0
0x82, // 54 LD Y // Y = 0
0x86, // 55 LD ADR_BUFFER10 // Low byte of the pointer 1 is used in the ECC calculate
0xa3, // 56 LD MSB 3 // ECC Mode & Reset TMP Reg, data_flash port = output
0xb9, // 57 LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // 58 LD CTRL_FCI // PARALLEL Port driven by FCI
0xaf, // 59 LD MSB 15
0xb4, // 5a LD LSB 4
0x84, // 5b LD ADR_BUFFER00 // ADR0 = 0x00F4, address of ECC1
//--------------------------
// Write one page to the SMC
//--------------------------
// :write_data_page
0xdc, // 5c LD A DATA_BUFFER1
0x8c, // 5d LD DATA_FLASH
0x9d, // 5e LD ECC_CRC // load ECC_CRC REG
0x2, // 5f CLC // Clear carry
0x31, // 60 XOR // Update carry
0xdd, // 61 LD A ECC_CRC // AUTO UPDATE OF Line PARITY 1
0xdd, // 62 LD A ECC_CRC // AUTO UPDATE OF Line PARITY 2
0xdd, // 63 LD A ECC_CRC // AUTO UPDATE OF column PARITY
0xc8, // 64 LD A CMP00
0x90, // 65 LD DR_PARALLEL
0xba, // 66 LD LSB 10
0x90, // 67 LD DR_PARALLEL
0x2f, // 68 ADDER16 ADR_BUFFER1 // Low byte of the pointer1 is using on ECC calculate
0x3d, // 69 INCY
// JP :write_data_page
0x6e, // 6a JP -14
//------------------
// Save the ECC code
//------------------
0xde, // 6b LD A TMP_ECC // first read (Line parity 1)
0x9b, // 6c LD DATA_BUFFER0
0xdd, // 6d LD A ECC_CRC // -- INCR CRC_ECC_STATE --
0x27, // 6e ADDER16 ADR_BUFFER0
0xde, // 6f LD A TMP_ECC // second read (Line parity 2)
0x9b, // 70 LD DATA_BUFFER0
0xdd, // 71 LD A ECC_CRC // -- INCR CRC_ECC_STATE --
0x27, // 72 ADDER16 ADR_BUFFER0
0xde, // 73 LD A TMP_ECC // third read ( column parity)
0x9b, // 74 LD DATA_BUFFER0
//------------------------------------------------------------------------------
// 256 bytes written to the SMC, goint to write the next 256 bytes
// ADR_BUFFER11 will change from 0001 -> 0010 -> 0011 when writing buffer0
// from 0011 -> 0100 -> 0101 when writing buffer1
//------------------------------------------------------------------------------
0xae, // 75 LD MSB 14
0xbf, // 76 LD LSB 15
0x84, // 77 LD ADR_BUFFER00 // ADR0 = 0x00EF, points to ECC2
0xc7, // 78 LD A ADR_BUFFER11
0x28, // 79 BCLR1
// JP :write_data_page
0x7e, // 7a JP -30
// :init_write_spare_area
//---------------------
0xae, // 7b LD MSB 14
0xb7, // 7c LD LSB 7
0x84, // 7d LD ADR_BUFFER00 // ADR0 = 0x00E7, points to the spare area
0xa0, // 7e LD MSB 0
0xbf, // 7f LD LSB 15
0x82, // 80 LD Y // Y = 0x0F
//-------------------------
// Write the redundant area
//-------------------------
// :write_spare_area
0xdb, // 81 LD A DATA_BUFFER0
0x8c, // 82 LD DATA_FLASH
0x27, // 83 ADDER16 ADR_BUFFER0
0xc8, // 84 LD A CMP00
0x90, // 85 LD DR_PARALLEL
0xba, // 86 LD LSB 10
0x90, // 87 LD DR_PARALLEL
0x3c, // 88 DECY
// JP :write_spare_area
0x68, // 89 JP -8
0x5, // 8a STATUS STOP
//------------------------------------------------------------------
// START ADDRESS OF SMC_DTC_SEND_CMD
// 0x1630 = The command to be sent
//------------------------------------------------------------------
0xa1, // 8b LD MSB 1 //data_flash port = output
0xb9, // 8c LD LSB 9 //DATA_FLASH Port driven by FCI
0x8d, // 8d LD CTRL_FCI //PARALLEL Port driven by FCI
0xaf, // 8e LD MSB 15
0xbf, // 8f LD LSB 15
0x83, // 90 LD MASK
0x31, // 91 XOR
0x85, // 92 LD ADR_BUFFER01
0xae, // 93 LD MSB 14
0x84, // 94 LD ADR_BUFFER00 // buffer pointer 0 = 0x00E0
0xdb, // 95 LD A DATA_BUFFER0 // load the command
0x8c, // 96 LD DATA_FLASH // send the command
0xa0, // 97 LD MSB 0
0xba, // 98 LD LSB 10 // WE = 1, CLE = 0
0x90, // 99 LD DR_PARALLEL
0xbb, // 9a LD LSB 11 // WE = 1, CLE = 1
0x90, // 9b LD DR_PARALLEL
0xb9, // 9c LD LSB 9 // WE = 0, CLE = 1
0x90, // 9d LD DR_PARALLEL
0xbb, // 9e LD LSB 11 // WE = 1, CLE = 1
0x90, // 9f LD DR_PARALLEL
0xba, // a0 LD LSB 10 // ALE = 0, WE = 1, CLE = 0
0x90, // a1 LD DR_PARALLEL
0xb1, // a2 LD LSB 1
0x81, // a3 LD X // initialize X = 1
0x5, // a4 STATUS STOP
//--------------------------------------------------
// START ADDRESS FOR SMC_DTC_SEND_ADDR
// ST7: Give a 3 or 4 bytes address
// 0x1632 - 0x1635 = The address, big endien (0x00E2-0x00E5)
//--------------------------------------------------
0xa1, // a5 LD MSB 1 //data_flash port = output
0xb9, // a6 LD LSB 9 //DATA_FLASH Port driven by FCI
0x8d, // a7 LD CTRL_FCI //PARALLEL Port driven by FCI
0xae, // a8 LD MSB 14
0xb6, // a9 LD LSB 06
0x84, // aa LD ADR_BUFFER00 // buffer pointer 0 = 0x00E6
0xdb, // ab LD A DATA_BUFFER0
0x82, // ac LD Y // Y = number of address bytes
0x3c, // ad DECY
0xbc, // ae LD LSB 12
0x89, // af LD CMP01 // CMP01 = 12, for send address toggling lines
0xbe, // b0 LD LSB 14
0x90, // b1 LD DR_PARALLEL // ALE = 1, WE = 1
0xc5, // b2 LD A ADR_BUFFER01 // clear A as the first byte, it is always 0
// loop_send_address
// -----------------
// :loop_send_address
0x26, // b3 SUB16 ADR_BUFFER0 // send address from high byte to low byte
0x8c, // b4 LD DATA_FLASH
0xc9, // b5 LD A CMP01
0x90, // b6 LD DR_PARALLEL // ALE = 1, WE = 0
0xbe, // b7 LD LSB 14
0x90, // b8 LD DR_PARALLEL // ALE = 1, WE = 1
0xdb, // b9 LD A DATA_BUFFER0
0x3c, // ba DECY
// JP :loop_send_address
0x68, // bb JP -8
0xa0, // bc LD MSB 0
0xba, // bd LD LSB 10 // ALE = 0, WE = 1, CLE = 0
0x90, // be LD DR_PARALLEL
0x5, // bf STATUS STOP
//-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
// Read Card ID
//-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-
//-------------------------------------
// START ADDRESS FOR Read_ID
//-------------------------------------
0xc5, // c0 LD A ADR_BUFFER01
0x9f, // c1 LD BUFFER_MNGT // clear segment offset
0x8c, // c2 LD DATA_FLASH // output the address
0xbe, // c3 LD LSB 14
0x90, // c4 LD DR_PARALLEL // ALE = 1, WE = 1
0xbc, // c5 LD LSB 12
0x90, // c6 LD DR_PARALLEL // ALE = 1, WE = 0
0xbe, // c7 LD LSB 14
0x90, // c8 LD DR_PARALLEL // ALE = 1, WE = 1
0xba, // c9 LD LSB 10
0x90, // ca LD DR_PARALLEL // ALE = 0, WE = 1, CLE = 0
0xb9, // cb LD LSB 9 // DATA_FLASH Port driven by FCI
//LD MSB 0 // DATA_FLASH Port = intput
0x8d, // cc LD CTRL_FCI // PARALLEL Port driven by FCI
0xaf, // cd LD MSB 15
0xbc, // ce LD LSB 12
0x82, // cf LD Y // Y = 0xFC
0xa0, // d0 LD MSB 0
0xb2, // d1 LD LSB 2
0x90, // d2 LD DR_PARALLEL // RD = 0
0xba, // d3 LD LSB 10
0x90, // d4 LD DR_PARALLEL // RD = 1
0xcc, // d5 LD A DATA_FLASH
0x80, // d6 LD <Y> // save the maker code
0x3d, // d7 INCY
0xa0, // d8 LD MSB 0
0xb2, // d9 LD LSB 2
0x90, // da LD DR_PARALLEL // RD = 0
0xba, // db LD LSB 10
0x90, // dc LD DR_PARALLEL // RD = 1
0xcc, // dd LD A DATA_FLASH
0x80, // de LD <Y> // save the device code
0x5, // df STATUS STOP
//-------------------------------------
// START ADDRESS FOR Read_Status
//-------------------------------------
0xc5, // e0 LD A ADR_BUFFER01
0x9f, // e1 LD BUFFER_MNGT // clear segment offset
0x86, // e2 LD ADR_BUFFER10
0x87, // e3 LD ADR_BUFFER11 // Buffer pointer 1 = 0x0000
0x8b, // e4 LD CMP11
0xb1, // e5 LD LSB 1
0x8a, // e6 LD CMP10 // CMP1 = 0x0001
// :read_status_loop
0x2f, // e7 ADDER16 ADR_BUFFER1
0xf, // e8 CP ADR_BUFFER1<CMP1
// JP :read_status_return
0x52, // e9 JP 18
0xa0, // ea LD MSB 0 // DATA_FLASH Port = intput
0xb9, // eb LD LSB 9 // DATA_FLASH Port driven by FCI
0x8d, // ec LD CTRL_FCI // PARALLEL Port driven by FCI
0xb2, // ed LD LSB 2
0x90, // ee LD DR_PARALLEL
0xaf, // ef LD MSB 15
0xbe, // f0 LD LSB 14
0x82, // f1 LD Y
0xcc, // f2 LD A DATA_FLASH // Get the status byte
0x80, // f3 LD <Y>
0xa0, // f4 LD MSB 0
0xba, // f5 LD LSB 10
0x90, // f6 LD DR_PARALLEL
0xc0, // f7 LD A <Y>
0x33, // f8 EXCHANGE
0x2a, // f9 BCLR3 // Check busy bit?
// JP :read_status_loop
0x73, // fa JP -19
// :read_status_return
//------------------
0x5, // fb STATUS STOP
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