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📄 new_copypages256_fsm.hex

📁 HID-Ukey底层源码实现(st72651芯片) windows上层驱动
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 ; *****************************************************************
 ; * NOTICE: The information contained in this file is proprietary *
 ; * to SGS-THOMSON Microelectronics and is being made available   *
 ; * to ST customers under strict non-disclosure agreements.       *
 ; * Use or disclosure of this information is permissible only     *
 ; * under the terms of the existing non-disclosure agreement.     *
 ; *****************************************************************

 ; Written by Christophe BRICOUT
 ; Created by MPmanCompiler.exe (v3.0) Tue Sep 27 12:18:47 2005


 ;===================================================================
 ;                    SMART MEDIA CARD
 ;	New_CopyPages256.fsm
 ;===================================================================
 ;	0xE0~0xE4	Source address
 ;	0xDB~0xDF	Destination address
 ;	0xDA		Flag of partial copy
 ;		D0: 1 = to do partial copy
 ;		D1: 1 = partial copy is needed
 ;		Initialization:	Pre-copy 0x00DA = 11, Post-copy 0x00DA = 10
 ;	0xD8,0xD9	Start column of partial copy
 ;	0xD6,0xD7	Length of partial copy
 ;	0xFF		Number of big pages
 ;-------------------------------
  
 0xa0,   ;   0 LD	MSB 0
 0xb1,   ;   1 LD	LSB 1
 0x81,   ;   2 LD	X			; X<=1
  
 0xb0,   ;   3 LD	LSB 0
 0x85,   ;   4 LD	ADR_BUFFER01
 0x87,   ;   5 LD	ADR_BUFFER11
 0x86,   ;   6 LD	ADR_BUFFER10
 0x31,   ;   7 XOR
 0x83,   ;   8 LD	MASK			; MASK = 0xFF
  
 ;-----------------
 ;init_dtc_ctrl_reg
 ;-----------------
 0xa1,   ;   9 LD	MSB 1			; data_flash port = output   
 0xb9,   ;   a LD	LSB 9			; DATA_FLASH Port driven by FCI 
 0x8d,   ;   b LD	CTRL_FCI		; PARALLEL Port driven by FCI
  
 ;-------------------------------
 ;command_latch_cycle (Read1 CMD)
 ;-------------------------------
 0xc5,   ;   c LD	A ADR_BUFFER01
 0x8c,   ;   d LD	DATA_FLASH		; Output CMD = 0x00
  
 0xba,   ;   e LD	LSB 10
 0x90,   ;   f LD	DR_PARALLEL
 0xbb,   ;  10 LD	LSB 11
 0x90,   ;  11 LD	DR_PARALLEL
 0xb9,   ;  12 LD	LSB 9
 0x90,   ;  13 LD	DR_PARALLEL
 0xbb,   ;  14 LD	LSB 11
 0x90,   ;  15 LD	DR_PARALLEL
  
 ;send address, set ALE high
 ;------------------------------
 0xbe,   ;  16 LD	LSB 14
 0x90,   ;  17 LD	DR_PARALLEL
  
 0xae,   ;  18 LD	MSB 14
 0xb4,   ;  19 LD	LSB 04
 0x84,   ;  1a LD	ADR_BUFFER00		; buffer pointer 0 = 0x00E4
 0xa0,   ;  1b LD	MSB 0
 0x82,   ;  1c LD	Y			; Y = 4 = number of address bytes
 0x8a,   ;  1d LD	CMP10			; Save this byte for destination address
  
 ; :loop_send_address
 ;-----------------
 0xdb,   ;  1e LD	A DATA_BUFFER0
 0x8c,   ;  1f LD	DATA_FLASH		; Output the address bytes
 0xbc,   ;  20 LD	LSB 12
 0x90,   ;  21 LD	DR_PARALLEL		; ALE = 1, WE = 0
 0xbe,   ;  22 LD	LSB 14
 0x90,   ;  23 LD	DR_PARALLEL		; ALE = 1, WE = 1
 0x26,   ;  24 SUB16	ADR_BUFFER0		; send address from high byte to low byte
  
 0x3c,   ;  25 DECY
 ; JP :loop_send_address
 0x68,   ;  26 JP  -8
  
 0xba,   ;  27 LD	LSB 10
 0x90,   ;  28 LD	DR_PARALLEL		; ALE = 0, WE = 1
  
 ;---------------------
 ;wait_read1_addr_ready
 ;---------------------
 0xa3,   ;  29 LD	MSB 3
 0xb5,   ;  2a LD	LSB 5
 0x8c,   ;  2b LD	DATA_FLASH		; Output CMD = 0x35
  
 0xbb,   ;  2c LD	LSB 11
 0x90,   ;  2d LD	DR_PARALLEL
 0xb9,   ;  2e LD	LSB 9
 0x90,   ;  2f LD	DR_PARALLEL
 0xbb,   ;  30 LD	LSB 11
 0x90,   ;  31 LD	DR_PARALLEL
 0xba,   ;  32 LD	LSB 10
 0x90,   ;  33 LD	DR_PARALLEL 
  
 ; :wait_read1_addr_ready
 ;---------------------
 0xd0,   ;  34 LD	A DR_PARALLEL
 0x33,   ;  35 EXCHANGE
 0x28,   ;  36 BCLR1				; Check Ready/Busy
 ; JP :wait_read1_addr_ready
 0x63,   ;  37 JP  -3
  
 ;send next command for copy operation 0x85
 ;-------------------------------------------
 0xa8,   ;  38 LD	MSB 8
 0xb5,   ;  39 LD	LSB 5
 0x8c,   ;  3a LD	DATA_FLASH		; Output CMD = 0x85
  
 0xbb,   ;  3b LD	LSB 11
 0x90,   ;  3c LD	DR_PARALLEL
 0xb9,   ;  3d LD	LSB 9
 0x90,   ;  3e LD	DR_PARALLEL
 0xbb,   ;  3f LD	LSB 11
 0x90,   ;  40 LD	DR_PARALLEL
  
 0xbe,   ;  41 LD	LSB 14
 0x90,   ;  42 LD	DR_PARALLEL
  
 ;send the address of destination block
 ;--------------------------------------
 0xca,   ;  43 LD	A CMP10
 0x82,   ;  44 LD	Y			; Y = number of address bytes
  
 ; :loop_send_address1
 ;-----------------
 0xdb,   ;  45 LD	A DATA_BUFFER0
 0x8c,   ;  46 LD	DATA_FLASH		; Output the destination address bytes
 0xbc,   ;  47 LD	LSB 12
 0x90,   ;  48 LD	DR_PARALLEL		; ALE = 1, WE = 0
 0xbe,   ;  49 LD	LSB 14
 0x90,   ;  4a LD	DR_PARALLEL		; ALE = 1, WE = 1
 0x26,   ;  4b SUB16	ADR_BUFFER0		; send address from high byte to low byte
  
 0x3c,   ;  4c DECY
 ; JP :loop_send_address1
 0x68,   ;  4d JP  -8
  
 0xba,   ;  4e LD	LSB 10
 0x90,   ;  4f LD	DR_PARALLEL		; ALE = 0, WE = 1
  
 ;------------------------------------------------
 ;Check if we need to leave some blank small pages
 ;------------------------------------------------
 0xdb,   ;  50 LD	A DATA_BUFFER0		; (0x00DA)
 0x28,   ;  51 BCLR1
 ; JP	:JP_start_pgm_cycle
 0x52,   ;  52 JP  18
 0x29,   ;  53 BCLR2
 ; JP	:JP_start_pgm_cycle
 0x50,   ;  54 JP  16
  
 0x9b,   ;  55 LD	DATA_BUFFER0		; Clear (0x00DA)
 0x26,   ;  56 SUB16	ADR_BUFFER0
  
 ;;;; Random data input command 0x85
 0xa8,   ;  57 LD	MSB 8
 0xb5,   ;  58 LD	LSB 5
 0x8c,   ;  59 LD	DATA_FLASH
  
 0xbb,   ;  5a LD	LSB 11
 0x90,   ;  5b LD	DR_PARALLEL
 0xb9,   ;  5c LD	LSB 9
 0x90,   ;  5d LD	DR_PARALLEL
 0xbb,   ;  5e LD	LSB 11
 0x90,   ;  5f LD	DR_PARALLEL
 0xa0,   ;  60 LD	MSB 0
 0xb2,   ;  61 LD	LSB 2
 0x82,   ;  62 LD	Y
 ; JP	:Send_Col_AddressX
 0x47,   ;  63 JP  7
  
 ; :JP_start_pgm_cycle
 ; JP	:start_pgm_cycle
 0x5a,   ;  64 JP  26
  
 ; :Send_Col_Address
 0xdb,   ;  65 LD	A DATA_BUFFER0		; (0x00D9, 0x00D8)
 0x26,   ;  66 SUB16	ADR_BUFFER0
 0x8c,   ;  67 LD	DATA_FLASH		; Output the first address bytes
 0xbc,   ;  68 LD	LSB 12
 0x90,   ;  69 LD	DR_PARALLEL		; ALE = 1, WE = 0
 ; :Send_Col_AddressX
 0xbe,   ;  6a LD	LSB 14
 0x90,   ;  6b LD	DR_PARALLEL		; ALE = 1, WE = 1
 0x3c,   ;  6c DECY
 ; JP	:Send_Col_Address
 0x68,   ;  6d JP  -8
  
 0xba,   ;  6e LD	LSB 10
 0x90,   ;  6f LD	DR_PARALLEL
  
 ;;;;	Load the finish address
 0xdb,   ;  70 LD	A DATA_BUFFER0		; (0x00D7)
 0x26,   ;  71 SUB16	ADR_BUFFER0
 0x8a,   ;  72 LD	CMP10
 0xdb,   ;  73 LD	A DATA_BUFFER0		; (0x00D6)
 0x8b,   ;  74 LD	CMP11
  
 ; :write_dat_sec
 ;-------------
 0xc3,   ;  75 LD	A MASK
 0x8c,   ;  76 LD	DATA_FLASH
  
 0xb8,   ;  77 LD	LSB 8
 0x90,   ;  78 LD	DR_PARALLEL
  
 0xba,   ;  79 LD	LSB 10
 0x90,   ;  7a LD	DR_PARALLEL
  
 0x2f,   ;  7b ADDER16	ADR_BUFFER1
 0xf,   ;  7c CP	ADR_BUFFER1<CMP1
 ; JP :write_dat_sec
 0x68,   ;  7d JP  -8
  
 ;----------------------------
 ; :Page_Pgm_command_latch_cycle
 ;----------------------------
  
 ; :start_pgm_cycle
 ;----------------
 0xa1,   ;  7e LD	MSB 1
 0xb0,   ;  7f LD	LSB 0
 0x8c,   ;  80 LD	DATA_FLASH		; Output CMD = 0x10
  
 0xbb,   ;  81 LD	LSB 11
 0x90,   ;  82 LD	DR_PARALLEL
 0xb9,   ;  83 LD	LSB 9
 0x90,   ;  84 LD	DR_PARALLEL
 0xbb,   ;  85 LD	LSB 11
 0x90,   ;  86 LD	DR_PARALLEL
 0xba,   ;  87 LD	LSB 10
 0x90,   ;  88 LD	DR_PARALLEL
  
 ;---------------------------
 ; read_status & check_status
 ;---------------------------
 ; :wait_card_ready
 0xd0,   ;  89 LD	A DR_PARALLEL
 0x33,   ;  8a EXCHANGE
 0x28,   ;  8b BCLR1				; Check Ready/Busy
 ; JP	:wait_card_ready
 0x63,   ;  8c JP  -3
  
 ; :read_status_command_latch_cycle
 ;-------------------------------
 0xa7,   ;  8d LD	MSB 7
 0xb0,   ;  8e LD	LSB 0
 0x8c,   ;  8f LD	DATA_FLASH		; Output CMD = 0x70
  
 0xbb,   ;  90 LD	LSB 11
 0x90,   ;  91 LD	DR_PARALLEL
 0xb9,   ;  92 LD	LSB 9
 0x90,   ;  93 LD	DR_PARALLEL
 0xbb,   ;  94 LD	LSB 11
 0x90,   ;  95 LD	DR_PARALLEL
 0xba,   ;  96 LD	LSB 10
 0x90,   ;  97 LD	DR_PARALLEL
  
 ; :init_read_status_seq
 ;---------------------
 0xa0,   ;  98 LD	MSB 0
 0xb9,   ;  99 LD	LSB 9			; DATA_FLASH Port driven by FCI  
 0x8d,   ;  9a LD	CTRL_FCI		; PARALLEL Port driven by FCI
  
 ; :read_status_seq
 ;----------------
 0xb2,   ;  9b LD	LSB 2
 0x90,   ;  9c LD	DR_PARALLEL
 0xba,   ;  9d LD	LSB 10
 0x90,   ;  9e LD	DR_PARALLEL
 0xcc,   ;  9f LD	A DATA_FLASH		; load DATA_FLASH
  
 ; :check_status
 ;-------------
 0x28,   ;  a0 BCLR1				; Test the LSB (D0==0?)
 ; JP	:no_error
 0x42,   ;  a1 JP  2
  
 ; :error_status
 ;------------
 0x7,   ;  a2 STATUS ERROR STOP
  
 ; :no_error
 ;--------
 0xc3,   ;  a3 LD	A MASK
 0x84,   ;  a4 LD	ADR_BUFFER00
 0xdb,   ;  a5 LD	A DATA_BUFFER0		; ADR0 = 0x00ff, contains 2K page pointer
 0x2,   ;  a6 CLC
 0x24,   ;  a7 SUB8	X
 0x9b,   ;  a8 LD	DATA_BUFFER0		; Save back
 0x8,   ;  a9 CP	A=>X
 ; JP	:dec_512_page
 0x42,   ;  aa JP  2
 0x5,   ;  ab STATUS STOP			; if 0 then stop
  
 ; :dec_512_page
 ;------------
 0x24,   ;  ac SUB8	X
 0x8,   ;  ad CP	A=>X			; Check if one page left
 ; JP	:increment_page
 0x47,   ;  ae JP  7
 0xad,   ;  af LD	MSB 13
 0xba,   ;  b0 LD	LSB 10
 0x84,   ;  b1 LD	ADR_BUFFER00
 0xdb,   ;  b2 LD	A DATA_BUFFER0		; (0x00DA)
 0x38,   ;  b3 BSET1
 0x9b,   ;  b4 LD	DATA_BUFFER0		; Set the partial copy flag
  
 ; :increment_page
 ;--------------- 
 ;; Decrease the page number and increase the page address
 0xae,   ;  b5 LD	MSB 14
 0xb2,   ;  b6 LD	LSB 2
 0x84,   ;  b7 LD	ADR_BUFFER00
 0xdb,   ;  b8 LD	A DATA_BUFFER0
 0x2,   ;  b9 CLC
 0x25,   ;  ba ADDER8	X
 0x9b,   ;  bb LD	DATA_BUFFER0		; Increase the source address and save it back
 ;------------------------------
 0xad,   ;  bc LD	MSB 13
 0xbd,   ;  bd LD	LSB 13
 0x84,   ;  be LD	ADR_BUFFER00
 0xdb,   ;  bf LD	A DATA_BUFFER0
 0x2,   ;  c0 CLC
 0x25,   ;  c1 ADDER8 X
 0x9b,   ;  c2 LD	DATA_BUFFER0		; Increase the destination address and save it back
 ;------------------------------
 0xc5,   ;  c3 LD	A ADR_BUFFER01		; Jump back to address 0x00
 0xb,   ;  c4 CP	ALWAYS
 0x60,   ;  c5 BRANCH

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