smc_dtc_upload_end.hex

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 // *****************************************************************
 // * NOTICE: The information contained in this file is proprietary *
 // * to SGS-THOMSON Microelectronics and is being made available   *
 // * to ST customers under strict non-disclosure agreements.       *
 // * Use or disclosure of this information is permissible only     *
 // * under the terms of the existing non-disclosure agreement.     *
 // *****************************************************************

 // Written by Christophe BRICOUT
 // Created by MPmanCompiler.exe (v3.0) Fri Apr 19 09:51:38 2002


 //===================================================================
 //
 //                    SMART MEDIA CARD
 //
 //===================================================================
  
 //------------
 // smc_dtc_up
 //------------
  
 //------------------------------------------------------------------
 //		START ADDRESS FOR read data to USB
 //	ST7: Give a 3 or 4 bytes address, number of pages
 //	0x1632 - 0x1635 = The address, big endien (0x00E2-0x00E5)
 //	0x163F = Number of pages (counter), it should be 0 on exit
 //	On return: Counter = 0 means no error
 //		   Counter !=0 means ECC error on that page
 //------------------------------------------------------------------
 // :init_command_address
 0xa1,   //   0 LD	MSB 1		// data_flash port = output
 0xb9,   //   1 LD	LSB 9		// DATA_FLASH Port driven by FCI  
 0x8d,   //   2 LD	CTRL_FCI	// PARALLEL Port driven by FCI
  
 0xa0,   //   3 LD	MSB 0
 0xbf,   //   4 LD	LSB 15
 0x91,   //   5 LD	DDR_PARALLEL	// PA3-0 as output, PA4 as input
 0x92,   //   6 LD	OR_PARALLEL	// PA3=/RD, PA2=ALE, PA1=/WE, PA0=CLE
  
  
 0xaf,   //   7 LD	MSB 15
 0x83,   //   8 LD	MASK		// MASK = 0xFF
  
 0x31,   //   9 XOR			// A = 0
 0x85,   //   a LD	ADR_BUFFER01	// clear the high byte of ADR0
 0x8c,   //   b LD	DATA_FLASH	// command Read(1), sequential read
  
 0xb1,   //   c LD	LSB 1
 0x81,   //   d LD	X		// X = 1
 0x87,   //   e LD	ADR_BUFFER11
  
 ////// Output the sequential read command (0x00)
 0xba,   //   f LD	LSB 10
 0x90,   //  10 LD	DR_PARALLEL	// WE = 1, CLE = 0
 0xbb,   //  11 LD	LSB 11
 0x90,   //  12 LD	DR_PARALLEL	// WE = 1, CLE = 1
 0xb9,   //  13 LD	LSB 9
 0x90,   //  14 LD	DR_PARALLEL	// WE = 0, CLE = 1
 0xbb,   //  15 LD	LSB 11
 0x90,   //  16 LD	DR_PARALLEL	// WE = 1, CLE = 1
 0xba,   //  17 LD	LSB 10
 0x90,   //  18 LD	DR_PARALLEL	// WE = 1, CLE = 0
  
 //--------------------------------------------------
 //             START ADDRESS FOR address_latch_cycle
 //--------------------------------------------------
 0xae,   //  19 LD	MSB 14
 0xb6,   //  1a LD	LSB 06
 0x84,   //  1b LD	ADR_BUFFER00	// buffer pointer 0 = 0x00E6
 0xdb,   //  1c LD	A DATA_BUFFER0
 0x82,   //  1d LD	Y		// Y = number of address bytes
 0x3c,   //  1e DECY
 0xbc,   //  1f LD	LSB 12
 0x89,   //  20 LD	CMP01		// CMP01 = 12, for send address toggling lines
 0xbe,   //  21 LD	LSB 14
 0x90,   //  22 LD	DR_PARALLEL	// ALE = 1, WE = 1
  
 0xc5,   //  23 LD	A ADR_BUFFER01	// clear A as the first byte, it is always 0
 0x86,   //  24 LD	ADR_BUFFER10	// clear low byte of ADR1
 0x8a,   //  25 LD	CMP10		// clear low byte of CMP1
 0x9f,   //  26 LD	BUFFER_MNGT	// clear SEGment offset for using Y on ECC check
  
 // :loop_send_address
 //-----------------
  
 0x26,   //  27 SUB16	ADR_BUFFER0	// send address from high byte to low byte
  
 0x8c,   //  28 LD	DATA_FLASH	// Output the address bytes
 0xc9,   //  29 LD	A CMP01
 0x90,   //  2a LD	DR_PARALLEL	// ALE = 1, WE = 0
 0xbe,   //  2b LD	LSB 14
 0x90,   //  2c LD	DR_PARALLEL	// ALE = 1, WE = 1
  
 0xdb,   //  2d LD	A DATA_BUFFER0
  
 0x3c,   //  2e DECY
 // JP :loop_send_address
 0x68,   //  2f JP  -8
  
 0xa0,   //  30 LD	MSB 0
 0xba,   //  31 LD	LSB 10
 0x90,   //  32 LD	DR_PARALLEL	// ALE = 0, WE = 1
  
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 ////
 ////	Start to read one page
 //// 1. Test the READY/BUSY line is ready
 //// 2. Wait one of the buffer is free
 //// 3. Read the page data
 //// 4. Check the ECC
 //// 5. Submit the buffer to send the page data
 ////
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // :Wait_SMC_Ready
 //--------------
 0xc5,   //  33 LD	A ADR_BUFFER01
 0x89,   //  34 LD	CMP01
 0xb2,   //  35 LD	LSB 2
 0x88,   //  36 LD	CMP00		// CMP0 = 0x0002, will use for RD toggling
 0x84,   //  37 LD	ADR_BUFFER00	// buffer pointer 0 = 0x0002
  
 ////// Reset the ECC calculation machine
 //     LD	MSB 0		// data_flash port = intput   
 0xb9,   //  38 LD	LSB 9		// DATA_FLASH Port driven by FCI 
 0x8d,   //  39 LD	CTRL_FCI	// PARALLEL Port driven by FCI 
 0xa2,   //  3a LD	MSB 2		// ECC Mode & Reset TMP Reg
 0x8d,   //  3b LD	CTRL_FCI	// PARALLEL Port driven by FCI
  
 // :wait_ready_line
 //---------------
 0x27,   //  3c ADDER16	ADR_BUFFER0
 0xc,   //  3d CP	ADR_BUFFER0=>CMP0
 // JP :test_busy_line
 0x42,   //  3e JP  2
  
 0x7,   //  3f STATUS STOP ERROR		// return with error
 // :test_busy_line
 //--------------
 0xd0,   //  40 LD	A DR_PARALLEL
 0x33,   //  41 EXCHANGE
 0x28,   //  42 BCLR1
 // JP :wait_ready_line
 0x67,   //  43 JP  -7
  
 // :Init_Page_Reading
 //-----------------		// Initialize ADR0 for read ECC
 0xc6,   //  44 LD	A ADR_BUFFER10
 0x85,   //  45 LD	ADR_BUFFER01	// clear high byte of pointer 0
 0xaf,   //  46 LD	MSB 15
 0xb8,   //  47 LD	LSB 8
 0x84,   //  48 LD	ADR_BUFFER00	// ADR0 = 0x00F8, points the ECC memory
  
 ////////////////////////////////////////////////////////////////////////////////////
 //// Test and wait one of the buffer is full
 ////////////////////////////////////////////////////////////////////////////////////
 0xc7,   //  49 LD	A ADR_BUFFER11
 0x39,   //  4a BSET2
 // JP :wait_buffer1_full
 0x47,   //  4b JP  7
  
 0xb1,   //  4c LD	LSB 1
 0x87,   //  4d LD	ADR_BUFFER11	// buffer pointer 1 = 0x0100
  
 // :wait_buffer0_full
 //-----------------
 0xdf,   //  4e LD	A BUFFER_MNGT
 0x3a,   //  4f BSET3
 // JP :wait_buffer0_full
 0x62,   //  50 JP  -2
 // JP :read_one_page
 0x44,   //  51 JP  4
  
 // :wait_buffer1_full
 //-----------------
 0xdf,   //  52 LD	A, BUFFER_MNGT
 0x3b,   //  53 BSET4
 // JP :wait_buffer1_full
 0x62,   //  54 JP  -2
  
 // :read_one_page
 //-------------
 0xc6,   //  55 LD	A ADR_BUFFER10
 0x82,   //  56 LD	Y		// Clear Y
  
 // :read_256_bytes
 //--------------
 0xb2,   //  57 LD	LSB 2
 0x90,   //  58 LD	DR_PARALLEL	// RD = 0// WE = 1// ALE=CLE=0
 0xba,   //  59 LD	LSB 10
 0x90,   //  5a LD	DR_PARALLEL	// RD = 1// WE = 1// ALE=CLE=0
  
 0xcc,   //  5b LD	A DATA_FLASH	// Get the reading data byte
 0x9c,   //  5c LD	DATA_BUFFER1	// Save it in the buffer
 0x9d,   //  5d LD	ECC_CRC		// Load to ECC_CRC REG
  
 0xdd,   //  5e LD	A ECC_CRC	// AUTO UPDATE OF Line PARITY 1
 0xdd,   //  5f LD	A ECC_CRC	// AUTO UPDATE OF Line PARITY 2
 0xdd,   //  60 LD	A ECC_CRC	// AUTO UPDATE OF column PARITY 
  
 0x2f,   //  61 ADDER16	ADR_BUFFER1
 0x3d,   //  62 INCY
 // JP :read_256_bytes
 0x6c,   //  63 JP  -12
  
 //-------------------
 // Save the calculated ECC to 0xF8, 0xF9, 0xFA -- 0xFB, 0xFC, 0xFD
 //-------------------
 // :read_ecc_calcul
 0xde,   //  64 LD	A TMP_ECC	// first read (Line parity 1)
 0x9b,   //  65 LD	DATA_BUFFER0
 0xdd,   //  66 LD	A ECC_CRC	// -- INCR CRC_ECC_STATE --
 0x27,   //  67 ADDER16 ADR_BUFFER0
  
 0xde,   //  68 LD	A TMP_ECC	// second read (Line parity 2)
 0x9b,   //  69 LD	DATA_BUFFER0
 0xdd,   //  6a LD	A ECC_CRC	// -- INCR CRC_ECC_STATE --
 0x27,   //  6b ADDER16 ADR_BUFFER0
  
 0xde,   //  6c LD	A TMP_ECC	// third read ( column parity)
 0x9b,   //  6d LD	DATA_BUFFER0
 0x27,   //  6e ADDER16	ADR_BUFFER0
  
 0xc7,   //  6f LD	A ADR_BUFFER11	// The value can be 0010, 0011, 0100, 0101
 0x28,   //  70 BCLR1
 // JP :read_256_bytes
 0x7a,   //  71 JP  -26
  
 //---------------------------------------------
 // Read 16 bytes of redundant area from the SMC
 // They will be saved in 0xE7-0xF6
 //---------------------------------------------
 // :init_read_spare
 0xbf,   //  72 LD	LSB 15
 0x82,   //  73 LD	Y		// Y = 15
 0xae,   //  74 LD	MSB 14
 0xb6,   //  75 LD	LSB 06
 0x84,   //  76 LD	ADR_BUFFER00	// ADR0 = 0x00E6,
  
 // :read_spare
 //----------
 0x27,   //  77 ADDER16	ADR_BUFFER0
  
 0xb2,   //  78 LD	LSB 2
 0x90,   //  79 LD	DR_PARALLEL	// RD = 0// WE = 1// ALE=CLE=0
 0xba,   //  7a LD	LSB 10
 0x90,   //  7b LD	DR_PARALLEL	// RD = 1// WE = 1// ALE=CLE=0
  
 0xcc,   //  7c LD	A DATA_FLASH	// Save one byte of redundant area
 0x9b,   //  7d LD	DATA_BUFFER0
  
 0x3c,   //  7e DECY
 // JP :read_spare
 0x68,   //  7f JP  -8
  
 //------------------------------------------------------
 // Check the calculated ECC againest with redundant area
 //------------------------------------------------------
 // :init_ecc2_check
 //---------------
 0xaf,   //  80 LD	MSB 15
 0xba,   //  81 LD	LSB 10
 0x82,   //  82 LD	Y		// Y = 0xFA, points to ECC2[2]
 0xb4,   //  83 LD	LSB 4
 0x88,   //  84 LD	CMP00		// CMP0 = 0x00F4
  
 // :ecc2_check
 //----------
 0xdb,   //  85 LD	A DATA_BUFFER0	// ADR0 = spare area = 0x00F6, 0x00F5, 0x00F4
 0x83,   //  86 LD	MASK
 0xc0,   //  87 LD	A <Y>		// Y = 0xFA, 0xF9, 0xF8
 0x31,   //  88 XOR
 0x8,   //  89 CP	A=>X
 // JP :ecc_error
 0x52,   //  8a JP  18
  
 0x26,   //  8b SUB16	ADR_BUFFER0
 0x3c,   //  8c DECY
 0xc,   //  8d CP	ADR_BUFFER0=>CMP0
 // JP :ecc2_check
 0x69,   //  8e JP  -9
  
 // :init_ecc1_check
 //---------------
 0xaf,   //  8f LD	MSB 15
 0xbd,   //  90 LD	LSB 13
 0x82,   //  91 LD	Y		// Y = 0xFD, points to ECC1[2]
 0xb0,   //  92 LD	LSB 0
 0x88,   //  93 LD	CMP00		// CMP0 = 0x00F0
 0x26,   //  94 SUB16	ADR_BUFFER0	// buffer pointer 0 = 0x00F2
  
 // :ecc1_check
 //----------
 0x26,   //  95 SUB16	ADR_BUFFER0
 0xdb,   //  96 LD	A DATA_BUFFER0	// buffer pointer 0 = 0x00F1, 0x00F0, 0x00EF
 0x83,   //  97 LD	MASK
 0xc0,   //  98 LD	A <Y>		// Y = 0xFD, 0xFC, 0xFB
 0x31,   //  99 XOR
 0x9,   //  9a CP	A<X
 // JP :no_ecc_error
 0x42,   //  9b JP  2
  
 // :ecc_error
 //---------
 0x5,   //  9c STATUS STATUS STOP
  
 // :no_ecc_error
 //------------
 0x3c,   //  9d DECY
 0xc,   //  9e CP	ADR_BUFFER0=>CMP0
 // JP :ecc1_check
 0x6a,   //  9f JP  -10
  
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 //// After the ECC check is verified. Submit the buffer read
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 0xc7,   //  a0 LD	A ADR_BUFFER11	// The value is either 0011 or 0101
 0x3a,   //  a1 BSET3
 // JP :Set_buffer1_full
 0x43,   //  a2 JP  3
  
 // :Set_buffer0_full
 //----------------
 0xb1,   //  a3 LD	LSB 1
 // JP :Set_Buffer_Full
 0x42,   //  a4 JP  2
  
 // :Set_buffer1_full
 //----------------
 0xb2,   //  a5 LD	LSB 2
 // :Set_Buffer_Full
 //---------------
 0x9f,   //  a6 LD	BUFFER_MNGT
 0xb0,   //  a7 LD	LSB 0
 0x9f,   //  a8 LD	BUFFER_MNGT
  
 // :next_page
 //---------
 0xaf,   //  a9 LD	MSB 15
 0xbf,   //  aa LD	LSB 15
 0x83,   //  ab LD	MASK
 0x84,   //  ac LD	ADR_BUFFER00	// buffer pointer 0 = 0x00FF, points the counter
 0xdb,   //  ad LD	A DATA_BUFFER0
 0x2,   //  ae CLC
 0x24,   //  af SUB8	X
 0x9b,   //  b0 LD	DATA_BUFFER0	// update the page counter
 0x8,   //  b1 CP	A=>X
 0xa3,   //  b2 LD	MSB 3
 0xb3,   //  b3 LD	LSB 3
 0x60,   //  b4 BRANCH	:Wait_SMC_Ready
  
 // :all_pages_read
 //--------------
 // ** LD	A BUFFER_MNGT	// wait for 2 buffers are free
 // ** BSET3
 // ** JP :all_pages_read
 // ** BSET4
 // ** JP :all_pages_read
  
 0x5,   //  b5 STATUS	STOP		// FINISH SUCCESSFULLY!
  
  
 //------------------------------------------------------------------
 //		START ADDRESS FOR read data FF to USB
 //	ST7: Give number of pages
 //	0x163F = Number of pages (counter), it should be 0 on exit
 //	On return: Counter = 0 means no error
 //		   Counter !=0 means ECC error on that page
 //------------------------------------------------------------------
  
 0xa0,   //  b6 LD	MSB 0
 0xb0,   //  b7 LD	LSB 0
 0x86,   //  b8 LD	ADR_BUFFER10	// low byte of pointer 1
 0x85,   //  b9 LD	ADR_BUFFER01	// high byte of pointer 0
 0x8a,   //  ba LD	CMP10
 0xb1,   //  bb LD	LSB 1
 0x87,   //  bc LD	ADR_BUFFER11	// ADR1 = 0x0100
 0x81,   //  bd LD	X		// X = 1
 0xb5,   //  be LD	LSB 5
 0x8b,   //  bf LD	CMP11		// CMP1 = 0x0500
  
 0xaf,   //  c0 LD	MSB 15
 0xbf,   //  c1 LD	LSB 15
 0x84,   //  c2 LD	ADR_BUFFER00	// ADR00 = 0x00FF
  
 // :fill_buffer_with_FF
 0x9c,   //  c3 LD	DATA_BUFFER1
 0x2f,   //  c4 ADDER16	ADR_BUFFER1
 0xf,   //  c5 CP	ADR_BUFFER1<CMP1
 // JP :fill_buffer_with_FF
 0x63,   //  c6 JP  -3
  
 0xdb,   //  c7 LD	A DATA_BUFFER0
 0x82,   //  c8 LD	Y		// load the page counter
  
 // :FFsend_2_pages
 //--------------
 0x3c,   //  c9 DECY
 // JP :FFwait_for_buffer_0
 0x42,   //  ca JP  2
 // JP :FF_finish
 0x4a,   //  cb JP  10
  
 // :FFwait_for_buffer_0
 //-----------------
 0xdf,   //  cc LD	A BUFFER_MNGT
 0x3a,   //  cd BSET3
 // JP :FFwait_for_buffer_0
 0x62,   //  ce JP  -2
  
 0xb1,   //  cf LD	LSB 1
 0x9f,   //  d0 LD	BUFFER_MNGT	// mark buffer0 full
 0xb0,   //  d1 LD	LSB 0
 0x9f,   //  d2 LD	BUFFER_MNGT	// mark buffer0 full
  
 0x3c,   //  d3 DECY
 // JP :FFwait_for_buffer_1
 0x45,   //  d4 JP  5
  
 // :FF_finish
 0x3d,   //  d5 INCY
 0xc2,   //  d6 LD	A Y
 0x9b,   //  d7 LD	DATA_BUFFER0	// clear the page counter
 0x5,   //  d8 STATUS	STOP
  
 // :FFwait_for_buffer_1
 //-----------------
 0xdf,   //  d9 LD	A BUFFER_MNGT
 0x3b,   //  da BSET4
 // JP :FFwait_for_buffer_1
 0x62,   //  db JP  -2
  
 0xb2,   //  dc LD	LSB 2
 0x9f,   //  dd LD	BUFFER_MNGT	// mark buffer1 full
 0xb0,   //  de LD	LSB 0
 0x9f,   //  df LD	BUFFER_MNGT	// mark buffer1 full
  
 // JP :FFsend_2_pages
 0x77,   //  e0 JP  -23

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