smc_dtc_debug_end.hex

HID-Ukey底层源码实现（st72651芯片） windows上层驱动

 // *****************************************************************
 // * NOTICE: The information contained in this file is proprietary *
 // * to SGS-THOMSON Microelectronics and is being made available   *
 // * to ST customers under strict non-disclosure agreements.       *
 // * Use or disclosure of this information is permissible only     *
 // * under the terms of the existing non-disclosure agreement.     *
 // *****************************************************************

 // Written by Christophe BRICOUT
 // Created by MPmanCompiler.exe (v3.0) Wed Mar 26 22:44:37 2003


 //===================================================================
 //
 //                    SMART MEDIA CARD
 //
 //===================================================================
  
 //------------
 // smc_dtc_up
 //------------
  
 //------------------------------------------------------------------
 //		START ADDRESS FOR read data to USB
 //	ST7: Give a 3 or 4 bytes address, number of pages
 //	0x1632 - 0x1635 = The address, big endien (0x00E2-0x00E5)
 //	0x163F = Number of pages (counter), it should be 0 on exit
 //	On return: Counter = 0 means no error
 //		   Counter !=0 means ECC error on that page
 //------------------------------------------------------------------
 // :init_command_address
 //      LD	MSB 1		// data_flash port = output
 //      LD	LSB 9		// DATA_FLASH Port driven by FCI  
 //      LD	CTRL_FCI	// PARALLEL Port driven by FCI
  
 0xa0,   //   0 LD	MSB 0
 0xbf,   //   1 LD	LSB 15
 0x91,   //   2 LD	DDR_PARALLEL	// PA3-0 as output, PA4 as input
 0x92,   //   3 LD	OR_PARALLEL	// PA3=/RD, PA2=ALE, PA1=/WE, PA0=CLE
  
  
 0xaf,   //   4 LD	MSB 15
 0x83,   //   5 LD	MASK		// MASK = 0xFF
  
 0x31,   //   6 XOR			// A = 0
 0x85,   //   7 LD	ADR_BUFFER01	// clear the high byte of ADR0                  
  
 //      LD	A ADR_BUFFER01	// clear A as the first byte, it is always 0
  
 //for 256mb
 //----------
 0x86,   //   8 LD	ADR_BUFFER10	// clear low byte of ADR1
 0x8a,   //   9 LD	CMP10		// clear low byte of CMP1
 0x9f,   //   a LD	BUFFER_MNGT	// clear SEGment offset for using Y on ECC check
 0xb1,   //   b LD	LSB 1
 0x81,   //   c LD	X		// X = 1
 0x8b,   //   d LD CMP11 //flag to differentiate b/w src read or destination read
 0x87,   //   e LD	ADR_BUFFER11
  
 //--------              
 // :next_page256
 //--------------
  
 0xa1,   //   f LD	MSB 1		// data_flash port = output
 0xb9,   //  10 LD	LSB 9		// DATA_FLASH Port driven by FCI  
 0x8d,   //  11 LD	CTRL_FCI	// PARALLEL Port driven by FCI
  
 //      LD A ADR_BUFFER01     
 0xa0,   //  12 LD MSB 0
 0xb0,   //  13 LD LSB 0
 0x85,   //  14 LD ADR_BUFFER01
 0x8c,   //  15 LD	DATA_FLASH	// command Read(1), sequential read
  
 //      LD	LSB 1
 //      LD	X		// X = 1
 //      LD	ADR_BUFFER11
  
 ////// Output the sequential read command (0x00)
 0xba,   //  16 LD	LSB 10
 0x90,   //  17 LD	DR_PARALLEL	// WE = 1, CLE = 0
 0xbb,   //  18 LD	LSB 11
 0x90,   //  19 LD	DR_PARALLEL	// WE = 1, CLE = 1
 0xb9,   //  1a LD	LSB 9
 0x90,   //  1b LD	DR_PARALLEL	// WE = 0, CLE = 1
 0xbb,   //  1c LD	LSB 11
 0x90,   //  1d LD	DR_PARALLEL	// WE = 1, CLE = 1
 0xba,   //  1e LD	LSB 10
 0x90,   //  1f LD	DR_PARALLEL	// WE = 1, CLE = 0
  
 //--------------------------------------------------
 //             START ADDRESS FOR address_latch_cycle
 //--------------------------------------------------
  
 //      LD	A ADR_BUFFER01	// clear A as the first byte, it is always 0,for 256mb
 //      LD	ADR_BUFFER10	// clear low byte of ADR1
 //      LD	CMP10		// clear low byte of CMP1
 //      LD	BUFFER_MNGT	// clear SEGment offset for using Y on ECC check 
 // :send_address
 0xae,   //  20 LD	MSB 14
 0xb6,   //  21 LD	LSB 06
 0x84,   //  22 LD	ADR_BUFFER00	// buffer pointer 0 = 0x00E6
 0xdb,   //  23 LD	A DATA_BUFFER0
 0x82,   //  24 LD	Y		// Y = number of address bytes
 0x3c,   //  25 DECY
 0xbc,   //  26 LD	LSB 12
 0x89,   //  27 LD	CMP01		// CMP01 = 12, for send address toggling lines
 0xbe,   //  28 LD	LSB 14
 0x90,   //  29 LD	DR_PARALLEL	// ALE = 1, WE = 1
  
 //      LD	A ADR_BUFFER01	// clear A as the first byte, it is always 0,for 256mb
 //      LD	ADR_BUFFER10	// clear low byte of ADR1
 //      LD	CMP10		// clear low byte of CMP1
 //      LD	BUFFER_MNGT	// clear SEGment offset for using Y on ECC check 
  
 //for debug routine
 //---------------------
 //flag to differentiate between the source page read or destination page read
 0xcb,   //  2a LD A CMP11
 0x38,   //  2b BSET1
 // JP :start_address
 0x44,   //  2c JP  4
 0xae,   //  2d LD MSB 14
 0xbc,   //  2e LD LSB 12
 0x84,   //  2f LD ADR_BUFFER00
  
 // :start_address
 0x26,   //  30 SUB16	ADR_BUFFER0	// send address from high byte to low byte
  
 // :loop_send_address
 //-----------------
  
 //      SUB16	ADR_BUFFER0	// send address from high byte to low byte
 0xdb,   //  31 LD	A DATA_BUFFER0
 0x8c,   //  32 LD	DATA_FLASH	// Output the address bytes
 0xc9,   //  33 LD	A CMP01
 0x90,   //  34 LD	DR_PARALLEL	// ALE = 1, WE = 0
 0xbe,   //  35 LD	LSB 14
 0x90,   //  36 LD	DR_PARALLEL	// ALE = 1, WE = 1
  
 0x26,   //  37 SUB16	ADR_BUFFER0	// send address from high byte to low byte
 //      LD	A DATA_BUFFER0
  
 0x3c,   //  38 DECY
 // JP :loop_send_address
 0x68,   //  39 JP  -8
  
 0xa0,   //  3a LD	MSB 0
 0xba,   //  3b LD	LSB 10
 0x90,   //  3c LD	DR_PARALLEL	// ALE = 0, WE = 1
  
 //---------------------------------------------------
 //For 256 MB or 2K page send 0x30 command,
 //---------------------------------------------------
  
 //send 0x30 cmd      
  
 0xa3,   //  3d LD MSB 3
 0xb0,   //  3e LD LSB 0
 0x8c,   //  3f LD DATA_FLASH 
  
 0xba,   //  40 LD	LSB 10
 0x90,   //  41 LD	DR_PARALLEL	// WE = 1, CLE = 0
 0xbb,   //  42 LD	LSB 11
 0x90,   //  43 LD	DR_PARALLEL	// WE = 1, CLE = 1
 0xb9,   //  44 LD	LSB 9
 0x90,   //  45 LD	DR_PARALLEL	// WE = 0, CLE = 1
 0xbb,   //  46 LD	LSB 11
 0x90,   //  47 LD	DR_PARALLEL	// WE = 1, CLE = 1
 0xba,   //  48 LD	LSB 10
 0x90,   //  49 LD	DR_PARALLEL	// WE = 1, CLE = 0
  
  
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 ////
 ////	Start to read one page
 //// 1. Test the READY/BUSY line is ready
 //// 2. Wait one of the buffer is free
 //// 3. Read the page data
 //// 4. Check the ECC
 //// 5. Submit the buffer to send the page data
 ////
 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 // :Wait_SMC_Ready
 //--------------
 0xc5,   //  4a LD	A ADR_BUFFER01
 0x89,   //  4b LD	CMP01
 0xb2,   //  4c LD	LSB 2
 0x88,   //  4d LD	CMP00		// CMP0 = 0x0002, will use for RD toggling
 0x84,   //  4e LD	ADR_BUFFER00	// buffer pointer 0 = 0x0002
  
 ////// Reset the ECC calculation machine
 //     LD	MSB 0		// data_flash port = intput   
 0xb9,   //  4f LD	LSB 9		// DATA_FLASH Port driven by FCI 
 0x8d,   //  50 LD	CTRL_FCI	// PARALLEL Port driven by FCI 
 0xa2,   //  51 LD	MSB 2		// ECC Mode & Reset TMP Reg
 0x8d,   //  52 LD	CTRL_FCI	// PARALLEL Port driven by FCI
  
 // :wait_ready_line
 //---------------
 0x27,   //  53 ADDER16	ADR_BUFFER0
 0xc,   //  54 CP	ADR_BUFFER0=>CMP0
 // JP :test_busy_line
 0x42,   //  55 JP  2
  
 0x7,   //  56 STATUS STOP ERROR		// return with error
 // :test_busy_line
 //--------------
 0xd0,   //  57 LD	A DR_PARALLEL
 0x33,   //  58 EXCHANGE
 0x28,   //  59 BCLR1
 // JP :wait_ready_line
 0x67,   //  5a JP  -7
  
 // :Init_Page_Reading
 //-----------------		// Initialize ADR0 for read ECC
 0xc6,   //  5b LD	A ADR_BUFFER10
 0x85,   //  5c LD	ADR_BUFFER01	// clear high byte of pointer 0
 //      LD	MSB 15
 //      LD	LSB 8
 //      LD	ADR_BUFFER00	// ADR0 = 0x00F8, points the ECC memory
  
 ////////////////////////////////////////////////////////////////////////////////////
 //// Test and wait one of the buffer is full
 ////////////////////////////////////////////////////////////////////////////////////
 0xc7,   //  5d LD	A ADR_BUFFER11
 0x39,   //  5e BSET2
 // JP :read_one_page
 0x43,   //  5f JP  3
  
 0xb1,   //  60 LD	LSB 1
 0x87,   //  61 LD	ADR_BUFFER11	// buffer pointer 1 = 0x0100
  
 //:wait_buffer0_full
 //-----------------
 //      LD	A BUFFER_MNGT
 //      BSET3
 //      JP :wait_buffer0_full
 //      JP :read_one_page
  
 //:wait_buffer1_full
 //-----------------
 //      LD	A, BUFFER_MNGT
 //      BSET4
 //      JP :wait_buffer1_full
  
 // :read_one_page
 //-------------
 0xc6,   //  62 LD	A ADR_BUFFER10
 0x82,   //  63 LD	Y		// Clear Y
  
 // :read_256_bytes
 //--------------
 0xb2,   //  64 LD	LSB 2
 0x90,   //  65 LD	DR_PARALLEL	// RD = 0// WE = 1// ALE=CLE=0
 0xba,   //  66 LD	LSB 10
 0x90,   //  67 LD	DR_PARALLEL	// RD = 1// WE = 1// ALE=CLE=0
  
 0xcc,   //  68 LD	A DATA_FLASH	// Get the reading data byte
 0x9c,   //  69 LD	DATA_BUFFER1	// Save it in the buffer
 //      LD	ECC_CRC		// Load to ECC_CRC REG
  
 //      LD	A ECC_CRC	// AUTO UPDATE OF Line PARITY 1
 //      LD	A ECC_CRC	// AUTO UPDATE OF Line PARITY 2
 //      LD	A ECC_CRC	// AUTO UPDATE OF column PARITY 
  
 0x2f,   //  6a ADDER16	ADR_BUFFER1
 0x3d,   //  6b INCY
 // JP :read_256_bytes
 0x68,   //  6c JP  -8
  
 0xc7,   //  6d LD	A ADR_BUFFER11	// The value can be 0010, 0011, 0100, 0101
 0x28,   //  6e BCLR1
 // JP :read_256_bytes
 0x6b,   //  6f JP  -11
  
 //---------------------------------------------
 // Read 16 bytes of redundant area from the SMC
 // They will be saved in 0xE7-0xF6
 //---------------------------------------------
 //:init_read_spare
 0xbf,   //  70 LD	LSB 15
 0x82,   //  71 LD	Y		// Y = 15
 0xae,   //  72 LD	MSB 14
 0xbf,   //  73 LD	LSB 15
 0x84,   //  74 LD	ADR_BUFFER00	// ADR0 = 0x00f0
  
 0xcb,   //  75 LD A CMP11
 0x38,   //  76 BSET1
 // JP :read_spare
 0x44,   //  77 JP  4