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HID-Ukey底层源码实现（st72651芯片） windows上层驱动

;===================================================================
;
;                    SMART MEDIA CARD
;
;===================================================================
 
;----------------------
; dtc_smc_mark_page.fsm
;----------------------
 
;--------------------------
;init_write_number_of_block
;--------------------------
 
LD MSB 0
LD LSB 1
LD X ; X<=1
 
;-----------------
;init_dtc_ctrl_reg
;-----------------
 
LD MSB 1 ; data_flash port = output
LD LSB 9 ; DATA_FLASH Port driven by FCI 
LD CTRL_FCI ; PARALLEL Port driven by FCI
 
;-------------------------------
;command_latch_cycle (Read2 CMD)
;-------------------------------
;for 256mb
;----------
LD MSB 0
LD LSB 0
LD ADR_BUFFER01
LD BUFFER_MNGT
 
LD MSB 13
LD ADR_BUFFER00	;send first write command (0x80) from 0xd0
LD A DATA_BUFFER0
LD DATA_FLASH
 
LD MSB 0
LD LSB 10
LD DR_PARALLEL	; RD = 1, ALE = 0, WE = 1, CLE = 0
LD LSB 11
LD DR_PARALLEL	; RD = 1, ALE = 0, WE = 1, CLE = 1
LD LSB 9
LD DR_PARALLEL	; RD = 1, ALE = 0, WE = 0, CLE = 1
; :repeat
LD LSB 11
LD DR_PARALLEL	; RD = 1, ALE = 0, WE = 1, CLE = 1
LD LSB 10
LD DR_PARALLEL	; RD = 1, ALE = 0, WE = 1, CLE = 0
 
;for 256mb
;----------
LD MSB 12		;Set a Flag at 0xc0= 0x00 for the card with 2K page
LD LSB 0
LD Y
LD A <Y>
BCLR1		;if 256mb no second cmd is required, is 0 JP
;      LD Y
;      DECY
JP :send_address
 
;send 0x80 cmd for other FLash
 
; :process_continue1
;------------------
LD MSB 1		; data_flash port = output
LD LSB 9		; DATA_FLASH Port driven by FCI 
LD CTRL_FCI	; PARALLEL Port driven by FCI
 
LD MSB 8
LD LSB 0
LD DATA_FLASH
; :send_nxt_cmd
;-------------
LD LSB 10
LD DR_PARALLEL	; WE = 1, CLE = 0
LD LSB 11
LD DR_PARALLEL	; WE = 1, CLE = 1
LD LSB 9
LD DR_PARALLEL	; WE = 0, CLE = 1
LD LSB 11
LD DR_PARALLEL	; WE = 1, CLE = 1
LD LSB 10
LD DR_PARALLEL	; WE = 1, CLE = 0
 
;-----------------
;init_dtc_ctrl_reg
;-----------------
 
;     LD MSB 1		; data_flash port = output
;     LD LSB 9		; DATA_FLASH Port driven by FCI
;     LD CTRL_FCI	; PARALLEL Port driven by FCI
 
; :send_address
LD MSB 0
LD LSB 0
LD ADR_BUFFER01
LD MSB 14
LD LSB 06
LD ADR_BUFFER00	; buffer pointer 0 = 0x00E6
LD A DATA_BUFFER0
LD Y		; Y = number of address bytes
DECY
LD LSB 12
LD CMP01		; CMP01 = 12, for send address toggling lines
 
LD LSB 14
LD DR_PARALLEL	; ALE = 1, WE = 1
 
;      LD A ADR_BUFFER01	; clear A as the first byte, it is always 0,for 256mb
;      LD ADR_BUFFER10	; clear low byte of ADR1
;      LD CMP10		; clear low byte of CMP1
;      LD BUFFER_MNGT	; clear SEGment offset for using Y on ECC check 
SUB16 ADR_BUFFER0	; send address from high byte to low byte
 
; :loop_send_address
;-----------------
 
;      SUB16 ADR_BUFFER0	; send address from high byte to low byte
LD A DATA_BUFFER0
LD DATA_FLASH	; Output the address bytes
LD A CMP01
LD DR_PARALLEL	; ALE = 1, WE = 0
LD LSB 14
LD DR_PARALLEL	; ALE = 1, WE = 1
 
SUB16 ADR_BUFFER0	; send address from high byte to low byte
;      LD A DATA_BUFFER0
 
DECY
JP :loop_send_address
 
LD MSB 0
LD LSB 10
LD DR_PARALLEL	; ALE = 0, WE = 1 
 
;---------------------
;wait_sdi_addr_ready
;---------------------
 
; :init_timeout
;------------
;      LD LSB 00
;      LD ADR_BUFFER01		; buffer 0 address ( 8..15 )
;      LD ADR_BUFFER00		; buffer 0 address ( 0..7 )
;      LD CMP00
;      LD MSB 15
;      LD CMP01
 
; :wait_sdi_addr_ready
;---------------------
;      ADDER16 ADR_BUFFER0
;      CP ADR_BUFFER0<CMP0
;      JP :sdi_addr_no_timeout
;      STATUS STOP ERROR   ; timeout >20ms
 
; :sdi_addr_no_timeout
;---------------------
;      LD A DR_PARALLEL
;      EXCHANGE
;      BCLR1 //test R/B
;      JP :wait_sdi_addr_ready
 
;------------
; write_spare
;------------
 
;init_write_spare
;----------------
 
LD MSB 0
LD LSB 0
LD ADR_BUFFER01		; buffer 0 address ( 15..8 )
LD CMP01
 
LD MSB 14
LD LSB 07
LD ADR_BUFFER00
 
LD MSB 15
LD CMP00
 
; :write_spare
;-----------
 
LD A DATA_BUFFER0
LD DATA_FLASH
 
LD MSB 0
LD LSB 8
LD DR_PARALLEL
 
LD LSB 10
LD DR_PARALLEL
 
ADDER16 ADR_BUFFER0
CP ADR_BUFFER0<CMP0
JP :write_spare
 
LD MSB 15
LD LSB 15
LD ADR_BUFFER00		;point to 0xff
 
LD A DATA_BUFFER0
CLC
SUB8 X
LD DATA_BUFFER0
CP A<X			;changed for bug
LD MSB 9
LD LSB 15
BRANCH :program_page
 
LD MSB 12
LD LSB 0
LD ADR_BUFFER00
LD A DATA_BUFFER0
BSET1
 
;      JP :program_page
LD MSB 9
LD LSB 15
; :program_page1
BRANCH :program_page
 
LD MSB 14
LD LSB 4
LD ADR_BUFFER00
 
LD MSB 0
LD LSB 2
LD Y
 
LD A DATA_BUFFER0
CLC
ADDER8 Y
LD DATA_BUFFER0
 
LD MSB 1
LD LSB 0
LD Y
 
;      LD MSB 14
;      LD LSB 5
ADDER16 ADR_BUFFER0
;      LD ADR_BUFFER00
LD A DATA_BUFFER0
CLC
ADDER8 Y
LD DATA_BUFFER0
EXCHANGE
BSET3
JP :next_page
 
LD MSB 14
LD LSB 6
LD ADR_BUFFER00
;      LD MSB 13
;      LD LSB 2			;reload address bytes into 0xd2
;      LD Y
;      LD A DATA_BUFFER0
;      LD <Y>
 
LD MSB 0
LD LSB 2
LD DATA_BUFFER0		;load 2 in 0xe6 to change number of add bytes
 
;send 0x85 command for random data output
;----------------------------------------
 
LD MSB 8
LD LSB 5
LD DATA_FLASH
LD MSB 2
LD LSB 5
CP ALWAYS
BRANCH :send_nxt_cmd
 
;      LD MSB 6
;      LD LSB 9
;      BRANCH :write_next_col
 
; :next_page
LD MSB 13
LD LSB 2
LD Y 
LD MSB 14
LD LSB 6
LD ADR_BUFFER00
LD A <Y>
LD DATA_BUFFER0		;reload again the number of address bytes
 
;      LD MSB 14
;      LD LSB 5
SUB16 ADR_BUFFER0
LD A ADR_BUFFER01
LD DATA_BUFFER0
SUB16 ADR_BUFFER0
LD LSB 2
LD DATA_BUFFER0
 
;----------------------------
; :Page_Pgm_command_latch_cycle
;----------------------------
; :program_page
;-------------
 
LD MSB 1
LD LSB 0
LD DATA_FLASH
 
LD MSB 0
LD LSB 10
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL
 
;---------------------------
; read_status & check_status
;---------------------------
 
;wait_card_ready
;---------------
 
;init_timeout
;------------
LD LSB 00
LD ADR_BUFFER01
LD ADR_BUFFER00
LD CMP00
LD MSB 15
LD CMP01
 
; :wait_card_ready
;---------------
ADDER16 ADR_BUFFER0
CP ADR_BUFFER0<CMP0
JP :no_timeout
STATUS STOP ERROR		; timeout 20ms
 
; :no_timeout
;----------
LD A DR_PARALLEL
EXCHANGE
BCLR1 //test R/B
JP :wait_card_ready
 
; :read_status_command_latch_cycle
;-------------------------------
 
LD MSB 7
LD LSB 0
LD DATA_FLASH
 
LD MSB 0
LD LSB 10
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL
 
; :init_read_status_seq
;---------------------
 
LD MSB 0
LD LSB 9		; DATA_FLASH Port driven by FCI
LD CTRL_FCI	; PARALLEL Port driven by FCI
 
; :read_status_seq
;----------------
 
LD MSB 0
LD LSB 2
LD DR_PARALLEL
NOP
LD A DATA_FLASH		; load DATA_FLASH
 
; : check_status
;-------------
;      EXCHANGE
;      BCLR3
;      JP :error_status
;      BCLR4
;      JP :error_status
;      CP A<X
BCLR1
JP :no_error
 
; :error_status
;------------
STATUS STOP
 
; :no_error
;--------
LD MSB 0
LD LSB 10
LD DR_PARALLEL
 
;------------
;end_of_block
;------------
 
;inc_addr
;-------- 
;for 256mb
 
LD LSB 0
LD MSB 0
LD ADR_BUFFER01		; buffer 0 address ( 8..15 )
 
LD MSB 15
LD LSB 15
LD ADR_BUFFER00
 
LD A DATA_BUFFER0
CP A=>X
JP :inc_page_addr
STATUS STOP
 
; :inc_page_addr
;-------------
 
LD MSB 12
LD LSB 0
LD ADR_BUFFER00
 
LD A DATA_BUFFER0
BSET1
JP :512bytes_page
 
LD MSB 14
LD LSB 03
LD ADR_BUFFER00		; buffer 0 address ( 0..7 )
CP ALWAYS
JP :process_continue
 
; :512bytes_page
;-------------
LD MSB 14
LD LSB 04
LD ADR_BUFFER00
 
; :process_continue
;-----------------
LD A DATA_BUFFER0
CLC
ADDER8 X
LD DATA_BUFFER0
 
LD MSB 1
LD LSB 15
;      LD Y
;      LD A <Y>
CP ALWAYS
BRANCH :repeat