smc_dtc_copy_page.fsm

HID-Ukey底层源码实现（st72651芯片） windows上层驱动

 ;===================================================================
 ;
 ;                    SMART MEDIA CARD
 ;
 ;===================================================================


 ;===================================================================
 ; MOdified by HYJ in MCU Competence Centre Shanghai China
 ;===================================================================

                      ;----------------------
                      ; dtc_smc_copy_page.fsm
                      ;----------------------

;--------------------------
;init_write_number_of_block
;--------------------------

LD MSB 0
LD LSB 1
LD X         ; X<=1

;-----------------
;init_dtc_ctrl_reg
;-----------------

LD MSB 1     ; data_flash port = output   
LD LSB 9     ; DATA_FLASH Port driven by FCI 
LD CTRL_FCI  ; PARALLEL Port driven by FCI --->CTRL_FCI = 0x19;parallel, data port.

;-------------------------------
;command_latch_cycle (Read1 CMD)
;-------------------------------

LD MSB 0
LD LSB 0
LD DATA_FLASH   ; // port B = 0x00; DATA_FLASH = DB;

LD MSB 0
LD LSB 10
LD DR_PARALLEL  ; // /RE = 1,ALE = 0,/WE = 1, CLE = 0;
LD LSB 11
LD DR_PARALLEL  ;// 1011
LD LSB 9
LD DR_PARALLEL  ;// 1001  /WE = 0;
LD LSB 11
LD DR_PARALLEL  ; // 1011 / WE = 1; CLE not change.
LD LSB 10
LD DR_PARALLEL  ; // 1010;  // CLE = 0, issue Command 0x00

;-------------------------
; read_address_latch_cycle
;-------------------------

;read_address_latch_cycle_nb_Bytes
;---------------------------------

LD MSB 0
LD LSB 0
LD ADR_BUFFER01		; buffer 0 address ( 15..8 )

LD MSB 14
LD LSB 06
LD ADR_BUFFER00		; buffer 0 address ( 0..7 )

LD A DATA_BUFFER0
LD Y                    ; ADDRESS Count = (0xE6)

LD MSB 14
LD LSB 02
LD ADR_BUFFER00

LD MSB 0
LD LSB 10
LD DR_PARALLEL   ; // 1010;

LD LSB 14
LD DR_PARALLEL   ; // 1110  // ALE = 0; 

; read_loop_send_address
; -----------------
:read_loop_send_address

LD A DATA_BUFFER0
LD DATA_FLASH      ; // DB = ADDRESS

LD MSB 0
LD LSB 12
LD DR_PARALLEL  ; // 1100 ;/WE = 0; 

LD LSB 14
LD DR_PARALLEL  ;// 1110 ; /WE = 1;

ADDER16 ADR_BUFFER0  ; // ADDRESS =  ADDRESS + 1;
  
DECY            ; // Y--
LD A Y
CP A=>X         ; // A>= 0x01
JP :read_loop_send_address

LD LSB 10       ; // ADDRESS finish transferring. 
LD DR_PARALLEL

;---------------------
;wait_read1_addr_ready
;---------------------

;init_timeout
;------------
LD LSB 00
LD ADR_BUFFER01		; buffer 0 address ( 8..15 )
LD ADR_BUFFER00		; buffer 0 address ( 0..7 )
LD CMP00
LD MSB 15
LD CMP01

:wait_read1_addr_ready
;---------------------
ADDER16 ADR_BUFFER0
CP ADR_BUFFER0<CMP0
JP :read1_addr_no_timeout
STATUS STOP ERROR   ; timeout >20ms

:read1_addr_no_timeout
;---------------------
LD A DR_PARALLEL
EXCHANGE
BCLR1 ;test R/B
JP :wait_read1_addr_ready

; -------------------------------------------
; START ADDRESS FOR read_dat 528 Bytes Buff 0
; -------------------------------------------

;init_read_dat_sec_reg
;---------------------

LD MSB 2	; DATA_FLASH port = intput 
LD LSB 9     	; DATA_FLASH Port driven by FCI 
LD CTRL_FCI  	; PARALLEL Port driven by FCI

LD MSB 0
LD LSB 1
LD ADR_BUFFER11      ; buffer 1 address ( 15..8 )

LD LSB 0
LD ADR_BUFFER10      ; buffer 1 address ( 7..0 )

LD LSB 3
LD CMP11             ; cmp1 value ( 15..8 )

LD MSB 1
LD LSB 0
LD CMP10             ; cmp1 value ( 7..0 )

; read_dat_sec
;-------------
:read_dat_sec

LD MSB 0
LD LSB 2
LD DR_PARALLEL

LD LSB 10
LD DR_PARALLEL

LD A DATA_FLASH         ; load DATA_FLASH
LD DATA_BUFFER1

ADDER16 ADR_BUFFER1
CP ADR_BUFFER1<CMP1
JP :read_dat_sec

;---------------------
;wait_read_block_ready
;---------------------

;init_timeout
;------------
LD MSB 0
LD LSB 00
LD ADR_BUFFER01		; buffer 0 address ( 8..15 )
LD ADR_BUFFER00		; buffer 0 address ( 0..7 )
LD CMP00
LD MSB 15
LD CMP01

:wait_read_block_ready
;---------------------
ADDER16 ADR_BUFFER0
CP ADR_BUFFER0<CMP0
JP :wait_read_block_no_timeout
STATUS STOP ERROR   ; timeout >20ms

:wait_read_block_no_timeout
;--------------------------
LD A DR_PARALLEL
EXCHANGE
BCLR1 ;test R/B
JP :wait_read_block_ready

;-----------------
;init_dtc_ctrl_reg
;-----------------

LD MSB 1     ; data_flash port = output   
LD LSB 9     ; DATA_FLASH Port driven by FCI 
LD CTRL_FCI  ; PARALLEL Port driven by FCI

;-----------------------------
;command_latch_cycle (SDI CMD)
;-----------------------------

LD MSB 8
LD LSB 0
LD DATA_FLASH

LD MSB 0
LD LSB 10
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL

;--------------------
; address_latch_cycle
;--------------------

:address_latch_cycle_nb_Bytes
;----------------------------

LD MSB 00
LD LSB 00
LD ADR_BUFFER01		; buffer 0 address ( 8..15 )

LD MSB 14
LD LSB 06
LD ADR_BUFFER00

LD A DATA_BUFFER0
LD Y

LD MSB 14
LD LSB 07
LD ADR_BUFFER00

LD MSB 0
LD LSB 10
LD DR_PARALLEL

LD LSB 14
LD DR_PARALLEL

; loop_send_address
; -----------------
:loop_send_address

LD A DATA_BUFFER0
LD DATA_FLASH

LD MSB 0
LD LSB 12
LD DR_PARALLEL

LD LSB 14
LD DR_PARALLEL

ADDER16 ADR_BUFFER0
  
DECY
LD A Y
CP A=>X
JP :loop_send_address

LD LSB 10
LD DR_PARALLEL

; -------------------------
; write_dat 512 Bytes Buff 0
; -------------------------

;init_write_dat_buff0
;--------------------

LD MSB 0
LD LSB 1
LD ADR_BUFFER11      ; buffer 1 address ( 15..8 )

LD LSB 0
LD ADR_BUFFER10      ; buffer 1 address ( 7..0 )

:write_dat_sec
;-------------

LD LSB 8
LD DR_PARALLEL

LD A DATA_BUFFER1
LD DATA_FLASH 

LD MSB 0
LD LSB 10
LD DR_PARALLEL

ADDER16 ADR_BUFFER1
CP ADR_BUFFER1<CMP1
JP :write_dat_sec

;----------------------------
:Page_Pgm_command_latch_cycle
;----------------------------

LD MSB 1
LD LSB 0
LD DATA_FLASH

LD MSB 0
LD LSB 10
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL

;---------------------------
; read_status & check_status
;---------------------------

;wait_card_ready
;---------------

;init_timeout
;------------
LD LSB 00
LD ADR_BUFFER01
LD ADR_BUFFER00
LD CMP00
LD MSB 15
LD CMP01

:wait_card_ready
;---------------
ADDER16 ADR_BUFFER0
CP ADR_BUFFER0<CMP0
JP :no_timeout
STATUS STOP ERROR   ; timeout 20ms

:no_timeout
;----------
LD A DR_PARALLEL
EXCHANGE
BCLR1 ;test R/B
JP :wait_card_ready

:read_status_command_latch_cycle
;-------------------------------

LD MSB 7
LD LSB 0
LD DATA_FLASH

LD MSB 0
LD LSB 10
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL

:init_read_status_seq
;---------------------

LD MSB 0
LD LSB 9     ; DATA_FLASH Port driven by FCI  
LD CTRL_FCI  ; PARALLEL Port driven by FCI

:read_status_seq
;----------------

LD MSB 0
LD LSB 2
LD DR_PARALLEL
NOP
LD A DATA_FLASH         ; load DATA_FLASH

:check_status
EXCHANGE
BCLR3
JP :error_status
JP :no_error
BCLR4
JP :error_status
JP :no_error

:error_status
STATUS STOP

;-------------
: check_status
;BCLR1			; bit0 is 1
;JP :error_status
;JP :no_error
;-------------

:no_error
;--------
LD MSB 0
LD LSB 10
LD DR_PARALLEL

;------------
;end_of_block
;------------

;inc_addr
;--------

LD LSB 0
LD MSB 0
LD ADR_BUFFER01      ; buffer 0 address ( 8..15 )

LD MSB 14
LD LSB 03
LD ADR_BUFFER00      ; buffer 0 address ( 0..7 )

LD A DATA_BUFFER0
CLC
ADDER8 X
LD DATA_BUFFER0

LD MSB 14
LD LSB 08
LD ADR_BUFFER00      ; buffer 0 address ( 0..7 )

LD A DATA_BUFFER0
CLC
ADDER8 X
LD DATA_BUFFER0

LD LSB 15
LD MSB 15
LD ADR_BUFFER00      ; buffer 0 address ( 7..0 )

LD A DATA_BUFFER0
SUB8 X
LD DATA_BUFFER0

CP A=>X
JP :process_continue
STATUS STOP          ; end of process

:process_continue

LD MSB 0
LD LSB 3
CP ALWAYS
BRANCH