📄 new_copypages256.fsm
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;===================================================================
; SMART MEDIA CARD
; New_CopyPages256.fsm
;===================================================================
; 0xE0~0xE4 Source address
; 0xDB~0xDF Destination address
; 0xDA Flag of partial copy
; D0: 1 = to do partial copy
; D1: 1 = partial copy is needed
; Initialization: Pre-copy 0x00DA = 11, Post-copy 0x00DA = 10
; 0xD8,0xD9 Start column of partial copy
; 0xD6,0xD7 Length of partial copy
; 0xFF Number of big pages
;-------------------------------
LD MSB 0
LD LSB 1
LD X ; X<=1
LD LSB 0
LD ADR_BUFFER01
LD ADR_BUFFER11
LD ADR_BUFFER10
XOR
LD MASK ; MASK = 0xFF
;-----------------
;init_dtc_ctrl_reg
;-----------------
LD MSB 1 ; data_flash port = output
LD LSB 9 ; DATA_FLASH Port driven by FCI
LD CTRL_FCI ; PARALLEL Port driven by FCI
;-------------------------------
;command_latch_cycle (Read1 CMD)
;-------------------------------
LD A ADR_BUFFER01
LD DATA_FLASH ; Output CMD = 0x00
LD LSB 10
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
;send address, set ALE high
;------------------------------
LD LSB 14
LD DR_PARALLEL
LD MSB 14
LD LSB 04
LD ADR_BUFFER00 ; buffer pointer 0 = 0x00E4
LD MSB 0
LD Y ; Y = 4 = number of address bytes
LD CMP10 ; Save this byte for destination address
:loop_send_address
;-----------------
LD A DATA_BUFFER0
LD DATA_FLASH ; Output the address bytes
LD LSB 12
LD DR_PARALLEL ; ALE = 1, WE = 0
LD LSB 14
LD DR_PARALLEL ; ALE = 1, WE = 1
SUB16 ADR_BUFFER0 ; send address from high byte to low byte
DECY
JP :loop_send_address
LD LSB 10
LD DR_PARALLEL ; ALE = 0, WE = 1
;---------------------
;wait_read1_addr_ready
;---------------------
LD MSB 3
LD LSB 5
LD DATA_FLASH ; Output CMD = 0x35
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL
:wait_read1_addr_ready
;---------------------
LD A DR_PARALLEL
EXCHANGE
BCLR1 ; Check Ready/Busy
JP :wait_read1_addr_ready
;send next command for copy operation 0x85
;-------------------------------------------
LD MSB 8
LD LSB 5
LD DATA_FLASH ; Output CMD = 0x85
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 14
LD DR_PARALLEL
;send the address of destination block
;--------------------------------------
LD A CMP10
LD Y ; Y = number of address bytes
:loop_send_address1
;-----------------
LD A DATA_BUFFER0
LD DATA_FLASH ; Output the destination address bytes
LD LSB 12
LD DR_PARALLEL ; ALE = 1, WE = 0
LD LSB 14
LD DR_PARALLEL ; ALE = 1, WE = 1
SUB16 ADR_BUFFER0 ; send address from high byte to low byte
DECY
JP :loop_send_address1
LD LSB 10
LD DR_PARALLEL ; ALE = 0, WE = 1
;------------------------------------------------
;Check if we need to leave some blank small pages
;------------------------------------------------
LD A DATA_BUFFER0 ; (0x00DA)
BCLR1
JP :JP_start_pgm_cycle
BCLR2
JP :JP_start_pgm_cycle
LD DATA_BUFFER0 ; Clear (0x00DA)
SUB16 ADR_BUFFER0
;;;; Random data input command 0x85
LD MSB 8
LD LSB 5
LD DATA_FLASH
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD MSB 0
LD LSB 2
LD Y
JP :Send_Col_AddressX
:JP_start_pgm_cycle
JP :start_pgm_cycle
:Send_Col_Address
LD A DATA_BUFFER0 ; (0x00D9, 0x00D8)
SUB16 ADR_BUFFER0
LD DATA_FLASH ; Output the first address bytes
LD LSB 12
LD DR_PARALLEL ; ALE = 1, WE = 0
:Send_Col_AddressX
LD LSB 14
LD DR_PARALLEL ; ALE = 1, WE = 1
DECY
JP :Send_Col_Address
LD LSB 10
LD DR_PARALLEL
;;;; Load the finish address
LD A DATA_BUFFER0 ; (0x00D7)
SUB16 ADR_BUFFER0
LD CMP10
LD A DATA_BUFFER0 ; (0x00D6)
LD CMP11
:write_dat_sec
;-------------
LD A MASK
LD DATA_FLASH
LD LSB 8
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL
ADDER16 ADR_BUFFER1
CP ADR_BUFFER1<CMP1
JP :write_dat_sec
;----------------------------
:Page_Pgm_command_latch_cycle
;----------------------------
:start_pgm_cycle
;----------------
LD MSB 1
LD LSB 0
LD DATA_FLASH ; Output CMD = 0x10
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL
;---------------------------
; read_status & check_status
;---------------------------
:wait_card_ready
LD A DR_PARALLEL
EXCHANGE
BCLR1 ; Check Ready/Busy
JP :wait_card_ready
:read_status_command_latch_cycle
;-------------------------------
LD MSB 7
LD LSB 0
LD DATA_FLASH ; Output CMD = 0x70
LD LSB 11
LD DR_PARALLEL
LD LSB 9
LD DR_PARALLEL
LD LSB 11
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL
:init_read_status_seq
;---------------------
LD MSB 0
LD LSB 9 ; DATA_FLASH Port driven by FCI
LD CTRL_FCI ; PARALLEL Port driven by FCI
:read_status_seq
;----------------
LD LSB 2
LD DR_PARALLEL
LD LSB 10
LD DR_PARALLEL
LD A DATA_FLASH ; load DATA_FLASH
:check_status
;-------------
BCLR1 ; Test the LSB (D0==0?)
JP :no_error
:error_status
;------------
STATUS ERROR STOP
:no_error
;--------
LD A MASK
LD ADR_BUFFER00
LD A DATA_BUFFER0 ; ADR0 = 0x00ff, contains 2K page pointer
CLC
SUB8 X
LD DATA_BUFFER0 ; Save back
CP A=>X
JP :dec_512_page
STATUS STOP ; if 0 then stop
:dec_512_page
;------------
SUB8 X
CP A=>X ; Check if one page left
JP :increment_page
LD MSB 13
LD LSB 10
LD ADR_BUFFER00
LD A DATA_BUFFER0 ; (0x00DA)
BSET1
LD DATA_BUFFER0 ; Set the partial copy flag
:increment_page
;---------------
;; Decrease the page number and increase the page address
LD MSB 14
LD LSB 2
LD ADR_BUFFER00
LD A DATA_BUFFER0
CLC
ADDER8 X
LD DATA_BUFFER0 ; Increase the source address and save it back
;------------------------------
LD MSB 13
LD LSB 13
LD ADR_BUFFER00
LD A DATA_BUFFER0
CLC
ADDER8 X
LD DATA_BUFFER0 ; Increase the destination address and save it back
;------------------------------
LD A ADR_BUFFER01 ; Jump back to address 0x00
CP ALWAYS
BRANCH
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