h2reg.h

Vitesse 24port gigabit Switch Source Code

/*

    Copyright (c) 2002-2005 Vitesse Semiconductor Corporation "Vitesse".  
    All Rights Reserved.  Unpublished rights reserved under the copyright laws
    of the United States of America, other countries and international treaties.
    The software is provided without a fee. Permission to use, copy, store and 
    modify, the software and its source code is granted. Permission to integrate
    into other products, disclose, transmit and distribute the software in an
    absolute machine readable format (e.g. HEX file) is also granted. 

    The source code of the software may not be disclosed, transmitted or
    distributed without the written permission of Vitesse. The software and its
    source code may only be used in products utilizing a Vitesse VSC73xx product.
 
    This copyright notice must appear in any copy, modification, disclosure,
    transmission or distribution of the software. Vitesse retains all ownership,
    copyright, trade secret and proprietary rights in the software.  

    THIS SOFTWARE HAS BEEN PROVIDED "AS IS," WITHOUT EXPRESS OR IMPLIED WARRANTY
    INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR USE AND NON-INFRINGEMENT.

*/
#ifndef __H2REG_H__
#define __H2REG_H__

/* ************************************************************************ **
 *
 *
 * Switch chip blocks
 *
 *
 *
 * ************************************************************************ */

/* (For performance optimization shift block ids in position used in register
   interface) */
#define PORT       (1 << 5)
#define ANALYZER   (2 << 5)
#define MIIM       (3 << 5)
#define CAPTURE    (4 << 5)
#define ARBITER    (5 << 5)
#define HPORT      (6 << 5)
#define SYSTEM     (7 << 5)

/* ************************************************************************ **
 *
 *
 * Memory initialization
 *
 *
 *
 * ************************************************************************ */

#define MEMINIT    (3 << 5)

#define MEMINIT_SUBBLK  2




#define MAX_MEM        32
#define MEMINIT_EXCLUDE_MASK 0x00000006 /* mem id 1-2 */


/* ************************************************************************ **
 *
 *
 * Register addresses
 *
 *
 *
 * ************************************************************************ */

/* system registers */
#define SYS_CPUMODE             0x00
#define SYS_SIPAD               0x01
#define SYS_PIWIDTH             0x02
#define SYS_SGMII_TR_DBG        0x08
#define SYS_GLORESET            0x14
#define SYS_CHIPID              0x18
#define SYS_TIMECMP             0x24
#define SYS_SLOWDATA            0x2C
#define SYS_INTCTRL             0x30 /* Alias SYS_CPUCTRL */
#define SYS_CPUCTRL             0x30 /* Alias SYS_INTCTRL */
#define SYS_CAPCTRL             0x31
#define SYS_GPIO                0x34
#define SYS_SIMASTER            0x35
#define SYS_ICPU_CTRL           0x10
#define SYS_ICPU_ADDR           0x11
#define SYS_ICPU_DATA           0x12
#define SYS_HWSEM               0x13
#define SYS_ICPU_MBOX_VAL       0x15
#define SYS_ICPU_MBOX_SET       0x16
#define SYS_ICPU_MBOX_CLR       0x17
#define SYS_ICPU_RAM_CFG        0x19
#define SYS_ICPU_ROM_CFG        0x1A
#define SYS_ICPU_RAM_MAP        0x1B
#define SYS_ICPU_ROM_MAP        0x1C

/* MIIM registers */
#define MIIMSTAT                0x00
#define MIIMCMD                 0x01
#define MIIMDATA                0x02
#define MIIMPRES                0x03
#define MIIMSCAN                0x04
#define MIIMSRES                0x05

/* ANALYZER registers */
#define ANA_STORMLIMIT          0xAA
#define ANA_STORMLIMIT_ENA      0xAB


#define ANA_IFLODMASK           0x04
#define ANA_ANMOVED             0x08
#define ANA_ANAGEFIL            0x09
#define ANA_ANEVENTS            0x0A
#define ANA_ANCNTMSK            0x0B
#define ANA_ANCNTVAL            0x0C
#define ANA_LERNMASK            0x0D
#define ANA_UFLODMSK            0x0E
#define ANA_MFLODMSK            0x0F
#define ANA_RECVMASK            0x10
#define ANA_AGGRCNTL            0x20
#define ANA_AGGRMSKS            0x30
#define ANA_DSTMASKS            0x40
#define ANA_SRCMASKS            0x80
#define ANA_MACHDATA            0x06
#define ANA_MACLDATA            0x07
#define ANA_ADVLEARN            0x03
#define ANA_IFLODMASK           0x04
#define ANA_VLANMASK			0x05
#define ANA_ANAGEFIL            0x09
#define ANA_CAPENAB             0xA0
#define ANA_CAPQUEUE            0xA1
#define ANA_ARP_IP0             0xA5
#define ANA_ARP_IP1             0xA6
#define ANA_TCPUDP_PORTS        0xA7
#define ANA_MACACCES            0xB0
#define ANA_MACTINDX            0xC0
#define ANA_VLANACES            0xD0
#define ANA_VLANINDX            0xE0
#define ANA_AGENCNTL            0xF0

/*  ARBITER registers */
#define ARBEMPTY                0x0C
#define ARBDISC                 0x0E
#define ARB_RATEUNIT            0x18
#define ARB_BURSTPROP           0x15

/*  CPU CAPTURE registers */
#define CAPREADP                0x00
#define CAP_CAPRST              0xFF
#define CAP_SUBBLK_DATA         0
#define CAP_SUBBLK_STATUS       4

/* MAC registers */
#define PORT_MACCONF            0x00
#define PORT_MACHDXGAP          0x02
#define PORT_FCTXCONF           0x04
#define PORT_FCMACHI            0x08
#define PORT_FCMACLO            0x0C
#define PORT_MAXLEN             0x10
#define PORT_PCSCTRL            0x18
#define PORT_ADVPORTM           0x19
#define PORT_PCSSTAT            0x1C
#define PORT_TXUPDCFG           0x24

/* Shared FIFO registers */
#define PORT_CPUTXDAT           0xC0
#define PORT_MISCFIFO           0xC4
#define PORT_MISCSTAT           0xC8
#define PORT_FREEPOOL           0xD8
#define PORT_Q_FLOWC_WM         0xDE
#define PORT_Q_MISC_CONF        0xDF
#define PORT_Q_EGRESS_WM        0xE0
#define PORT_RATECONF           0x28

/* Categorizer registers */
#define PORT_CAT_PR_DSCP_QOS     0x60
#define PORT_CAT_PR_DSCP_VAL_0_3 0x61
#define PORT_CAT_PR_DSCP_VAL_4_6 0x62
#define PORT_CAT_DROP            0x6E
#define PORT_CAT_PR_MISC_L2      0x6F
#define PORT_CAT_PR_USR_PRIO     0x75
#define PORT_CAT_PR_MISC_L3      0x77
#define PORT_CAT_VLAN_MISC       0x79
#define PORT_CAT_PORT_VLAN       0x7A
/* Filter register */
#define PORT_FILTER_SIP_CONF     0x63
#define PORT_FILTER_SIP_ADDR     0x64

/* Statistics registers */

/* Detailed Statistics registers */
#define PORT_C_RXOCT            0x50
#define PORT_C_TXOCT            0x51
#define PORT_C_RX0              0x52
#define PORT_C_RX1              0x53
#define PORT_C_RX2              0x54
#define PORT_C_RX3              0x55
#define PORT_C_RX4              0x56

#define PORT_C_TX0              0x57
#define PORT_C_TX1              0x58
#define PORT_C_TX2              0x59
#define PORT_C_TX3              0x5a
#define PORT_C_TX4              0x5b

#define PORT_CNT_CTRL_CFG       0x5c
#define PORT_CNT_CTRL_CFG2      0x5d


/* MEMINIT registers */
#define MEMINIT_MEMINIT         0x00
#define MEMINIT_MEMRES          0x01


/* ************************************************************************ **
 *
 *
 * Bit mapping
 *
 *
 *
 * ************************************************************************ */


/* Port SRCMASKS register */
#define CPU_COPY_BIT          27
#define MIRROR_BIT            26

/* Analyzer AGENCNTL register */
#define MIRROR_PORT_MASK      0x0001F

/* Tx header for port CPUTXDAT register */
#define CPU_FRAME_LENGTH_BIT  16
#define CPU_FRAME_LENGTH_MASK 0x3fff

/* Analyzer MACTINDX register */
#define BUCKET_BIT            11

/* GPIO bits */
#define GPIO_0_BIT    0
#define GPIO_1_BIT    1
#define GPIO_2_BIT    2
#define GPIO_3_BIT    3
#define GPIO_OE_0_BIT 4
#define GPIO_OE_1_BIT 5
#define GPIO_OE_2_BIT 6
#define GPIO_OE_3_BIT 7

/* PHY reset release bit in GLORESET register */
#define PHY_RESET_RELEASE 1

/* Analyzer ADVLEARN register */
#define VLAN_CHK_BIT          29


/* Port (MAC) reset mask (for MACCONF register) */
#define MAC_RESET_MASK 0x2000083C

/* Define CLK_DIV in ICPU_CTRL register */
#define BASE_FREQ 178571428
#define CLK_DIV ((uchar) ((((float) BASE_FREQ / CLOCK_FREQ)  - 1) + 0.5))

#define CLK_DIV_MASK 0x00001F00

/* ************************************************************************ **
 *
 *
 * Miscellaneous
 *
 *
 *
 * ************************************************************************ */

/*
** Chip id
*/ 
#if !defined(LUTON_G16) && !defined(LUTON_G16R)
#define EXPECTED_CHIPID 0x073900E9
#elif !defined(LUTON_G16R)
#define EXPECTED_CHIPID 0x073890E9
#else
#define EXPECTED_CHIPID 0x073910E9
#endif
/*
** Maximum number of ports in a link aggregation group
*/ 

#if !defined(LUTON_G16) && !defined(LUTON_G16R)
#define MAX_NO_OF_AGGR_PORTS 12
#else
#define MAX_NO_OF_AGGR_PORTS 8
#endif




#endif