txrxtst.c

Vitesse 24port gigabit Switch Source Code

    do {

        port_no_1 = port_no;
        if (external_loopback) {
            port_no_2 = port_no + 1;
        }
        /*
        ** Run through speeds
        */
        memset(result, 0xff, sizeof(result));
        for (mode = (NO_OF_MODES - 1); mode != 0xff; mode--) {
            if (mode_mask & (1 << mode)) {


                if (mode <= 2) {
                    if (phy_map(port_no_1) && ((phy_map(port_no_2) && port_no_2 < MAX_PORT) || !external_loopback)) {    

                        if (external_loopback) {
                            if (mode < 2) {
                                init_phys_forced(port_no_1, port_no_2, mode);

                                loop_count_1 = 0;
                                loop_count_2 = 0;
                                while ((!phy_link_status(port_no_1) || !phy_link_status(port_no_2)) && 
                                       (loop_count_2 < 3)) {

                                    delay_1(10);
                                    loop_count_1++;
                                    if (loop_count_1 >= 250) {
                                        init_phys_forced(port_no_1, port_no_2, mode);
                                        loop_count_2++;
                                        loop_count_1 = 0;
                                    }
                                }
                            }
                        }
                        else {
                            phy_set_forced_speed(port_no_1, mode | LINK_MODE_FDX_MASK | LINK_MODE_INT_LOOPBACK);
                            delay(MSEC_100);
                        }

                        init_port(port_no_1, mode);
                        if (external_loopback) {
                            init_port(port_no_2, mode);
                        }
                        delay(MSEC_50);
                    }
                    else {
                        continue;
                    }
                }

                if (external_loopback) {
                    result[0] = (result[0] & ~(0x03 << (mode << 1))) | 
                    (test_tx_rx(port_no_1, port_no_2) << (mode << 1));
                    result[1] = (result[1] & ~(0x03 << (mode << 1))) | 
                        (test_tx_rx(port_no_2, port_no_1) << (mode << 1)); /* swap ports */
                }
                else {
                    result[0] = (result[0] & ~(0x03 << (mode << 1))) | 
                        (test_tx_rx(port_no_1, port_no_1) << (mode << 1));
                }
            }
        }

        /*
        ** Display results for 1 or 2 ports, and update port number
        */
        for (j = 0; (!external_loopback && j < 1) || (external_loopback && j < 2); j++) {
            print_cr_lf();
            print_spaces(4);
            print_dec_8_right_2(port_no);
            print_spaces(4);

            for (mode = 0; mode < NO_OF_MODES; mode++) {

                result_tmp = (result[j] >> (mode << 1)) & 0x03;

                if (result_tmp == 0x03) {
                    print_spaces(8); /* spaces in column if speed not tested */
                }
                else if (result_tmp == 0) {
                    print_str(txt_12); /* ok txt */
                }
                else {
                    print_str(txt_13); /* error txt */
                    print_dec(result_tmp);
                    print_ch(' ');
                }
            }

            /* Reset PHY and update port number */
            if (j == 0) {
                if (phy_map(port_no_1)) {
                    phy_reset(port_no_1);
                }
            }
            else {
                if (phy_map(port_no_2)) {
                    phy_reset(port_no_2);
                }
            }
            port_no++;
            if (port_no > port_no_stop) {
                break;
            }
        }

    } while (port_no <= port_no_stop);

    print_str(txt_14); /* completed message */

    h2_write(ANALYZER, 0, 13, ALL_PORTS);
    h2_write(ANALYZER, 0, 14, ALL_PORTS);
    h2_write(ANALYZER, 0, 15, ALL_PORTS);
}

static void init_port (uchar port_no, uchar mode)
{
    ulong reg_val_dw;

    h2_write(PORT, port_no, PORT_ADVPORTM, 0x00);  /* Remove any advanced setup */

    reg_val_dw = h2_build_mac_config(port_no, mode | LINK_MODE_FDX_MASK) | 0x10010000;

    h2_write(PORT, port_no, PORT_MACCONF, reg_val_dw | MAC_RESET_MASK);
    h2_write(PORT, port_no, PORT_MACCONF, reg_val_dw);
}

static void init_phys_forced (uchar port_no_1, uchar port_no_2, uchar mode)
{
    phy_reset(port_no_1);
    phy_reset(port_no_2);
    delay(MSEC_50);
    phy_set_forced_speed(port_no_1, mode | LINK_MODE_FDX_MASK);
    phy_set_forced_speed(port_no_2, mode | LINK_MODE_FDX_MASK);
}

/* ************************************************************************ */
static uchar test_tx_rx (uchar rx_port_no, uchar tx_port_no)
/* ------------------------------------------------------------------------ --
 * Purpose     : Send a frame on tx_port_no and receive the frame on rx_port_no.
 * Remarks     :
 * Restrictions:
 * See also    :
 * Example     :
 * ************************************************************************ */
{
    uchar result;

    h2_write(PORT, tx_port_no, PORT_TXUPDCFG, 0x06); /* Update CRC */

    /* Set analyzer to copy frame to CPU capture buffer */
    h2_write_bit(ANALYZER, 0, ANA_SRCMASKS + rx_port_no, CPU_COPY_BIT, 1);

    delay(MSEC_20);

    send_packet(tx_port_no);

    start_timer(MSEC_100);
    while (!h2_frame_received()) {
        if (timeout()) {
            break;
        }
    }
    if (!timeout()) {
        if (get_and_check_packet(rx_port_no, tx_port_no) == 0) {
            result = 0;
        }
        else {
            result = 1;
        }
    }
    else {
        result = 2;
    }

    /* Set analyzer to not copy frame to CPU capture buffer */
    h2_write_bit(ANALYZER, 0, ANA_SRCMASKS + rx_port_no, CPU_COPY_BIT, 0);

    return result;
}

/* ************************************************************************ */
static void send_packet (uchar port_no) 
/* ------------------------------------------------------------------------ --
 * Purpose     : Send packet.
 * Remarks     :
 * Restrictions:
 * See also    :
 * Example     :
 * ************************************************************************ */
{
    pac_len_t j;

    h2_tx_init(port_no, PACKET_LENGTH);

    for (j = 0; j < (((PACKET_LENGTH + 7) / 8) * 2); j++) {
        h2_tx_word(0x12345600 + port_no);
    }
    h2_tx_flush();
}

/* ************************************************************************ */
static uchar get_and_check_packet (uchar rx_port_no, uchar tx_port_no)
/* ------------------------------------------------------------------------ --
 * Purpose     : Get and check packet.
 * Remarks     :
 * Restrictions:
 * See also    :
 * Example     :
 * ************************************************************************ */
{
    pac_len_t j;
    uchar error;
    vtss_frm_hdr_t frm_hdr;

    error = FALSE;

    /* Check length and source port*/
    if (h2_rx_hdr(&frm_hdr) != PACKET_LENGTH) {
        error = TRUE;
    }
    if (frm_hdr.src_port != rx_port_no) {
        error = TRUE;
    }

    /* Read and check packet */
    if (!error) {
        for (j = 0; j < (PACKET_LENGTH / 4 - 1); j++) {
            if (h2_rx_word() != (0x12345600 + tx_port_no)) {
                error = TRUE;
            }
        }
    }

    /* Acknowledge packet */
    h2_rx_ack();

    return error;

}
#endif