spidrv.a51

Vitesse 24port gigabit Switch Source Code

;*
;*
;*    Copyright (c) 2002-2003 Vitesse Semiconductor Corporation "Vitesse".  
;*    All Rights Reserved.  Unpublished rights reserved under the copyright laws
;*    of the United States of America, other countries and international treaties.
;*    The software is provided without a fee. Permission to use, copy, store and 
;*    modify, the software and its source code is granted. Permission to integrate
;*    into other products, disclose, transmit and distribute the software in an
;*    absolute machine readable format (e.g. HEX file) is also granted. 
;*
;*    The source code of the software may not be disclosed, transmitted or
;*    distributed without the written permission of Vitesse. The software and its
;*    source code may only be used in products utilizing a Vitesse VSC73xx product.
;* 
;*    This copyright notice must appear in any copy, modification, disclosure,
;*    transmission or distribution of the software. Vitesse retains all ownership,
;*    copyright, trade secret and proprietary rights in the software.  
;*
;*    THIS SOFTWARE HAS BEEN PROVIDED "AS IS," WITHOUT EXPRESS OR IMPLIED WARRANTY
;*    INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY,
;*    FITNESS FOR A PARTICULAR USE AND NON-INFRINGEMENT.
;*
;*
$NOMOD51
$INCLUDE (REG52.INC)
$INCLUDE (hwconf.inc)

NAME    SPIMOD

$IF (USE_SI = 1)

PUBLIC  spi_init
PUBLIC  _spi_write
PUBLIC  _spi_read
PUBLIC  spi_built_in

SPI_BITS        SEGMENT BIT
                RSEG    SPI_BITS
spi_built_in:   DBIT    1       ; Flag whether the MCU has a built-in SPI module

PROG    SEGMENT CODE

        RSEG    PROG

;* Macro for transmitting one bit from bit 7 in acc register onto the SPI bus
tx_1_bit macro
        RLC     A
        MOV     MOSI, C
        SETB    SCK
        SPI_DELAY_1
        CLR     SCK
        endm

;* Macro for transmitting 8 bits from the acc register onto the SPI bus
tx_8_bit macro

        REPT    8
        tx_1_bit
        endm
        endm

;* Macro for receiving one bit from the SPI bus and shift it into the acc register
rx_1_bit macro
        SETB    SCK
        SPI_DELAY_1
        MOV     C, MISO
        RLC     A
        CLR     SCK
        SPI_DELAY_1
        endm

;* Macro for receiving 8 bits from the SPI bus and return them in the acc register
rx_8_bit macro

        REPT    8
        rx_1_bit
        endm
        endm

;* ************************************************************************ */
tx_byte_func:
;* ------------------------------------------------------------------------ --
;* Purpose     : Transmit a byte via built-in SPI module in MPU.
;* Remarks     : On entry register A must hold byte to be transmitted.
;* Restrictions: NOT c-compatible
;* See also    :
;* Example     :
; * ************************************************************************ */

        mov     b, a

        ; There seems to be a problem with SST89E564 that can
        ; be circumvented by disabling interrupt during SPI operation
        clr     ea

        mov     a, SPSR ; dummy read to clear bits
        ; Write value
L1_1:   mov     SPDR, b
        mov     a, SPSR
        jb      acc.6, L1_1
        jb      acc.7, L1_3

        ; Await completion of transfer
L1_2:   mov     a, SPSR
        jnb     acc.7, L1_2
L1_3:

        ; Enable interrupt again
        setb    ea

        ret

;* ************************************************************************ */
rx_byte_func:
;* ------------------------------------------------------------------------ --
;* Purpose     : Receive a byte via built-in SPI module in MPU.
;* Remarks     : The byte read is returned in register A
;* Restrictions: NOT c-compatible
;* See also    :
;* Example     :
; * ************************************************************************ */

        ; There seems to be a problem with SST89E564 that can
        ; be circumvented by disabling interrupt during SPI operation
        clr     ea

        ; Trig transfer by writing a dummy value to the SPI module
        mov     a, SPSR ; dummy read to clear bits
        mov     SPDR, a ; dummy write to issue clocks

        ; Await completion of transfer
L2_1:   mov     a, SPSR
        jnb     acc.7, L2_1

        ; return received value 
        mov     a, SPDR

        setb    ea      ; Enable interrupt again

        ret

;* ************************************************************************ */
; void  spi_init (void) small;
spi_init:
;* ------------------------------------------------------------------------ --
;* Purpose     : Deselect Heathrow and setup built-in SPI module in MCU if any.
;* Remarks     : 
;* Restrictions:
;* See also    :
;* Example     :
; * ************************************************************************ */
        setb    SS

        clr     spi_built_in
        ; The SPCR register of SST89E56 has default value 0x04. Assume this
        ; is sufficient to determine that MCU has built-in SPI module
        mov     a, SPCR
        cjne    a, #04, L3_1
        setb    spi_built_in
        mov     SPCR, #050H
L3_1:
        ret

;* ************************************************************************ */
; ulong  spi_read (uchar block, uchar subblock, uchar addr) small;
_spi_read:
;* ------------------------------------------------------------------------ --
;* Purpose     : Read specified register.
;* Remarks     : 
;* Restrictions: Must be called via h2io.a51
;* See also    :
;* Example     :
; * ************************************************************************ */

        ;* Build 1st byte to send.
        ;*--------------------------------------------------------------------
        mov     a, r7           ; block mask
        orl     a, r5           ; subblock

L4_2:   jnb     spi_built_in, L4_1

        ;* Use built-in SPI module
        ;*--------------------------------------------------------------------
        clr     SS              ; Enable SPI

        lcall   tx_byte_func
        mov     a, r3           ; register address
        lcall   tx_byte_func

        LCALL   rx_byte_func    ; Dummy byte

        LCALL   rx_byte_func    ; 1st byte
        mov     r4, a

        LCALL   rx_byte_func    ; 2nd byte
        mov     r5, a

        LCALL   rx_byte_func    ; 3rd byte
        mov     r6, a

        LCALL   rx_byte_func    ; 4th byte
        mov     r7, a

        setb    SS              ; Disable SPI

        ret

        ;* Use macros for controlling SPI signals
        ;*--------------------------------------------------------------------
L4_1:   clr     SCK
        clr     SS              ; Enable SPI

        tx_8_bit
        mov     a, r3           ; register address
        tx_8_bit

        rx_8_bit                ; 1st byte
        mov     r4, a

        rx_8_bit                ; 2nd byte
        mov     r5, a

        rx_8_bit                ; 3rd byte
        mov     r6, a

        rx_8_bit                ; 4th byte
        mov     r7, a

        setb    SS              ; Disable SPI

        ret

;* ************************************************************************ */
; void  spi_write (uchar *addr, ulong value) small;
_spi_write:
;* ------------------------------------------------------------------------ --
;* Purpose     : Write a value to specified register
;* Remarks     : r2:   block mask plus subblock
;*               r1:   register address
;*               r4-7: 32-bit value
;* Restrictions: Not C-compatible. Must be called via h2io.a51
;* See also    :
;* Example     :
; * ************************************************************************ */

        ;* Build 1st byte to send.
        ;*--------------------------------------------------------------------
        mov     a, r2           ; Get block and subblock
        orl     a, #10H         ; Set write command

        jnb     spi_built_in, L6_1

        ;* Use built-in SPI module
        ;*--------------------------------------------------------------------
        clr     SS              ; Enable SPI

        lcall   tx_byte_func
        mov     a, r1           ; register address
        lcall   tx_byte_func

        mov     a, r4
        lcall   tx_byte_func    ; 1st byte

        mov     a, r5
        lcall   tx_byte_func    ; 2nd byte

        mov     a, r6
        lcall   tx_byte_func    ; 3rd byte

        mov     a, r7
        lcall   tx_byte_func    ; 4th byte

        setb    SS              ; Disable SPI

        ret

        ;* Use macros for controlling SPI signals
        ;*--------------------------------------------------------------------
L6_1:   clr     SCK
        clr     SS              ; Enable SPI

        tx_8_bit
        mov     a, r1           ; register address
        tx_8_bit

        mov     a, r4
        tx_8_bit                ; 1st byte

        mov     a, r5
        tx_8_bit                ; 2nd byte

        mov     a, r6
        tx_8_bit                ; 3rd byte

        mov     a, r7
        tx_8_bit                ; 4th byte

        setb    SS              ; Disable SPI

        ret
$ENDIF
        END