phyconf.h

Vitesse 24port gigabit Switch Source Code

/*

    Copyright (c) 2003-2006 Vitesse Semiconductor Corporation "Vitesse".  
    All Rights Reserved.  Unpublished rights reserved under the copyright laws
    of the United States of America, other countries and international treaties.
    The software is provided without a fee. Permission to use, copy, store and 
    modify, the software and its source code is granted. Permission to integrate
    into other products, disclose, transmit and distribute the software in an
    absolute machine readable format (e.g. HEX file) is also granted. 

    The source code of the software may not be disclosed, transmitted or
    distributed without the written permission of Vitesse. The software and its
    source code may only be used in products utilizing a Vitesse VSC73xx product.
 
    This copyright notice must appear in any copy, modification, disclosure,
    transmission or distribution of the software. Vitesse retains all ownership,
    copyright, trade secret and proprietary rights in the software.  

    THIS SOFTWARE HAS BEEN PROVIDED "AS IS," WITHOUT EXPRESS OR IMPLIED WARRANTY
    INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR USE AND NON-INFRINGEMENT.

*/
#ifndef __PHYCONF_H__
#define __PHYCONF_H__


/* ************************************************************************ **
 *
 *
 * PHY ids
 *
 *
 *
 * ************************************************************************ */

#define PHY_OUI_VTSS_1   0x000fc400
#define PHY_OUI_VTSS_2   0x00070400


#define PHY_ID_VTSS_8558_A 0x00070580
#define PHY_ID_VTSS_8538_A 0x00070480

#define PHY_ID_VTSS_8558 0x00070780 /* no revision A/0 actually exists */
#define PHY_ID_VTSS_8538 0x00070680 /* no revision A/0 actually exists */

#define PHY_ID_VTSS_8201 0x000FC410
#define PHY_ID_VTSS_8204 0x000FC440

#define PHY_ID_VTSS_8224 0x000FC580
#define PHY_ID_VTSS_8234 0x000FC780
#define PHY_ID_VTSS_8244 0x000FC6C0

#define PHY_ID_VTSS_7391 0x00070510
#define PHY_ID_VTSS_7390 0x00070500
#define PHY_ID_VTSS_7389 0x00070490
#define PHY_ID_VTSS_7388 0x00070480
#define PHY_ID_VTSS_7385 0x00070450


/* ************************************************************************ **
 *
 *
 * Select PHY parts
 *
 *
 *
 * ************************************************************************ */

#define VTSS_8201 0
#define VTSS_8204 0
#define VTSS_8224 0
#define VTSS_8538 1


/*
** Miscellaneous
*/
#if VTSS_8204
#define CICADA_B5_FORCED_100_PATCH 1
#endif


/* ************************************************************************ **
 *
 *
 * Frame gap settings
 *
 *
 *
 * ************************************************************************ */


/* 
** Define frame gaps values to be used in MACCONF for actual PHYs
*/

#define TX_IPG_10            17
#define TX_IPG_100           17
#define TX_IPG_1000           6

/*
** Half duplex gaps
*/
#define RX_TX_IFG_1_10        6
#define RX_TX_IFG_1_100       6

#define RX_TX_IFG_2_10        8
#define RX_TX_IFG_2_100       8

#define LCOLPOS               2




/* ************************************************************************ **
 *
 *
 * Mode and clock settings
 *
 *
 *
 * ************************************************************************ */


/* No settings for SparX */



/* ************************************************************************ **
 *
 *
 * PHY mode settings
 *
 *
 *
 * ************************************************************************ */


#if VTSS_8204


#define VTSS_REG_23 0x1214  /* Enable RGMII */ /* Runway */


#elif VTSS_8224
#define VTSS_REG_23 0x1a24

#endif

/* ************************************************************************ **
 *
 *
 * Possibly macro for initializing PHY after reset
 *
 *
 *
 * ************************************************************************ */



/* ************************************************************************ **
 *
 *
 * Possibly macro for reading current speed and duplex of PHY
 *
 *
 *
 * ************************************************************************ */


/* 
** Define a macro that reads info about speed and duplex mode
** from the PHY associated with port_no.
** It must update link_mode bit 0 and 1 with the current speed:
** bit 1:0 = 00:   10 Mbit/s
** bit 1:0 = 01:  100 Mbit/s
** bit 1:0 = 10: 1000 Mbit/s
**
** and bit 4 with current duplex mode:
** bit 4 = 0: half duplex
** bit 4 = 1: full duplex
*/
#define PHY_READ_SPEED_AND_FDX(port_no, reg_val, link_mode) {     \
}


/* ************************************************************************ **
 *
 *
 * PHY LED settings
 *
 *
 *
 * ************************************************************************ */



#define PHY_LED_MODE     0x0000     //20070927 BY MOS
#define PHY_LED_MODE_SFP 0x7eee

/* ************************************************************************ **
 *
 *
 * PHY register 9 settings
 *
 *
 *
 * ************************************************************************ */

/*
** Define pattern to write to PHY register 9 for 1000BASE-T control.
*/
#if VTSS_8204
#define PHY_REG_9_CONFIG 0x0200
#else
#define PHY_REG_9_CONFIG 0x0600
#endif

/* ************************************************************************ **
 *
 *
 * Mapping between physical ports and PHYs
 *
 *
 *
 * ************************************************************************ */


#if !defined(LUTON_G16) && !defined(LUTON_G16R)


/*
** Define mapping between port numbers and PHYs. For each port specify the 
** PHY number of the PHY connected to the port. And for each port specify
** the MIIM number of the management bus for the connected PHY.

Luton port number:  
  0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,23
  ---------------------------------------------------------------------- */
#define PHY_MAP_PHY_NO  { \
  0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7,16,17,18,19,20,21,22,23}

#define PHY_MAP_MIIM_NO { \
  1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1}


#elif !defined(LUTON_G16R)

/*
** Define mapping between port numbers and PHYs. For each port specify the 
** PHY number of the PHY connected to the port. And for each port specify
** the MIIM number of the management bus for the connected PHY.

Luton port number:  
  0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15
  ---------------------------------------------- */
#define PHY_MAP_PHY_NO  { \
  0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7}

#define PHY_MAP_MIIM_NO { \
  1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}

#else

/*
** Define mapping between port numbers and PHYs. For each port specify the 
** PHY number of the PHY connected to the port. And for each port specify
** the MIIM number of the management bus for the connected PHY.

Luton port number:  
  0, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,11,12,13,14,15,16,17,18,19,20,21,22,23
  ---------------------------------------------------------------------- */
#define PHY_MAP_PHY_NO  { \
  0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7,16,17,18,19,20,21,22,23}

#define PHY_MAP_MIIM_NO { \
  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1}

#endif



/* ************************************************************************ **
 *
 *
 * Enabling/disabling of echo mode in 10 Mbps half-duplex
 *
 *
 *
 * ************************************************************************ */


/* 
** Define macros for disabling/enabling echo mode.
** On some PHYs echo mode must be disabled at 10 Mbps in half-duplex 
** mode to work together with the MAC.
*/

#define PHY_DISABLE_ECHO_MODE(port_no) \
    phy_write_masked(port_no, 0x16, (ushort) 1 << 13, (ushort) 1 << 13)

#define PHY_ENABLE_ECHO_MODE(port_no) \
    phy_write_masked(port_no, 0x16, (ushort) 0 << 13, (ushort) 1 << 13)


/* ************************************************************************ **
 *
 *
 * Enabling/disabling PHY id check
 *
 *
 *
 * ************************************************************************ */

/* 
** Define whether PHY ids should be checked as run-time check. 
** Set PHY_ID_CHECK to 1 to enable check, or to 0 to disable check.
*/
#define PHY_ID_CHECK 0

/* 
** Define PHY id to be checked if PHY_ID_CHECK is set to 1
** Set PHY_OUI_MSB to the expected value of register 2.
*/
#define PHY_OUI_MSB 0x0007



/* ************************************************************************ **
 *
 *
 * SFP module configuration
 *
 *
 *
 * ************************************************************************ */

/*
** Set SFP_NUM to number of SFP modules. If no SFPs, set it to 0, and the
** remaining SFP configuration is don't care.
*/
#define SFP_NUM 4

#define SFP_PORT_MASK ((port_bit_mask_t) 0x0000000F) /* ports 0-3 */

#define SFP_PORTS               { 0,  1,  2,  3}
#define SFP_MODULE_DETECT_GPIOS { 4,  5,  6,  7}
#define SFP_TX_DISABLE_GPIOS    { 9, 10, 11, 12}

#define SFP_MODULE_DETECT_GPIO_PORT 0
#define SFP_TX_DISABLE_GPIO_PORT    0
#define SFP_I2C_GPIO_PORT           0



#endif