hwconf.inc

Vitesse 24port gigabit Switch Source Code

;*
;*
;*    Copyright (c) 2004-2005 Vitesse Semiconductor Corporation "Vitesse".  
;*    All Rights Reserved.  Unpublished rights reserved under the copyright laws
;*    of the United States of America, other countries and international treaties.
;*    The software is provided without a fee. Permission to use, copy, store and 
;*    modify, the software and its source code is granted. Permission to integrate
;*    into other products, disclose, transmit and distribute the software in an
;*    absolute machine readable format (e.g. HEX file) is also granted. 
;*
;*    The source code of the software may not be disclosed, transmitted or
;*    distributed without the written permission of Vitesse. The software and its
;*    source code may only be used in products utilizing a Vitesse VSC73xx product.
;* 
;*    This copyright notice must appear in any copy, modification, disclosure,
;*    transmission or distribution of the software. Vitesse retains all ownership,
;*    copyright, trade secret and proprietary rights in the software.  
;*
;*    THIS SOFTWARE HAS BEEN PROVIDED "AS IS," WITHOUT EXPRESS OR IMPLIED WARRANTY
;*    INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY,
;*    FITNESS FOR A PARTICULAR USE AND NON-INFRINGEMENT.
;*
;*

;* ************************************************************************ **
;*
;*
;* Internal 8051 registers
;*
;*
;*
;* ************************************************************************ */

        ; Special SFRs
        GPIO_IN  DATA 080H
        SPC_FNC  DATA 08FH
        GPIO_OUT DATA 090H
        GPIO_OE  DATA 0A0H
        FPSTAT   DATA 0AAH
        PAGE_SEL DATA 0B0H
        EPAGE_SEL DATA 0C0H
        SPC_FNC2 DATA 0F1H
        RA_STAT  DATA 0F8H
        RA_BLK   DATA 0F9H
        RA_AD_RD DATA 0FAH
        RA_AD_WR DATA 0FBH
        RA_DA0   DATA 0FCH
        RA_DA1   DATA 0FDH
        RA_DA2   DATA 0FEH
        RA_DA3   DATA 0FFH

        RA_DONE  BIT  0F8H ; RA_STAT^0

        ; Paging bits
        PG_OP_0  BIT 0B0H
        PG_OP_1  BIT 0B1H
        PG_OP_2  BIT 0B2H
        PG_OP_3  BIT 0B3H
        PG_IFP_0 BIT 0B4H
        PG_IFP_1 BIT 0B5H
        PG_IFP_2 BIT 0B6H
        PG_IFP_3 BIT 0B7H



;* ************************************************************************ **
;*
;*
;* Select chip interface
;*
;*
;*
;* ************************************************************************ */

        ;* 
        ;* Define which chip interface to use, either 8-bit parallel interface,
        ;* SI interface or SFR interface.
        ;* Set USE_PI to 1 to use 8-bit interface, otherwise set it to 0.
        ;* Set USE_SI to 1 to use SI interface, otherwise set it to 0.
        ;* Set USE_SFR to 1 to use SFR interface, otherwise set it to 0.
        ;* Please, keep c-file hwconf.h updated accordingly.
        ;*
        $SET (USE_PI = 0)
        $SET (USE_SI = 0)
        $SET (USE_SFR = 1)

;* ************************************************************************ **
;*
;*
;* SPI configuration
;*
;*
;*
;* ************************************************************************ */

        ; SPI pins
        SS      BIT     094H    ; P1^4
        MOSI    BIT     095H    ; P1^5
        MISO    BIT     096H    ; P1^6
        SCK     BIT     097H    ; P1^7

        ; SPI registers present if the controller is e.g. a SST89V564
        SPCR    DATA    0D5H
        SPSR    DATA    0AAH
        SPDR    DATA    086H

SPI_DELAY_1 macro
        ; no delay needed
        endm

;* ************************************************************************ **
;*
;*
;* Select MOVX/MOVC for reading from flash pages
;*
;*
;*
;* ************************************************************************ */

        ;*
        ;* 0; movx
        ;* 1: movc
        ;*
        $SET (FAR_ACCESS_METHOD = 0)

;* ************************************************************************ **
;*
;*
;* Chip definitions used in assembler functions
;*
;*
;*
;* ************************************************************************ */

        ; Switch chip blocks with special handling in assembler
        LPORT_BLK_ID_MASK       EQU     020H
        HPORT_BLK_ID_MASK       EQU     0C0H
        CAPTURE_BLK_ID_MASK     EQU     080H
        SYSTEM_BLK_ID_MASK      EQU     0E0H

        ; Switch chip registers with special handling in assembler
        PORT_CPUTXDAT           EQU     0C0H
        PORT_MISCSTAT           EQU     0C8H

        SYS_CPUCTRL             EQU     030H
        SYS_GPIO                EQU     034H
        SYS_GLORESET            EQU     014H
        SYS_ICPU_RAM_MAP        EQU     01BH
        SYS_ICPU_ROM_MAP        EQU     01CH
        ; PI address of SLOWDATA register
        SLOWDATA_ADDR           EQU     0C0B0H

        ; GPIO bits (SYSTEM block register)
        GPIO_OE_3_BIT   EQU     7
        GPIO_OE_2_BIT   EQU     6
        GPIO_OE_1_BIT   EQU     5
        GPIO_OE_0_BIT   EQU     4
        GPIO_3_BIT      EQU     3
        GPIO_2_BIT      EQU     2
        GPIO_1_BIT      EQU     1
        GPIO_0_BIT      EQU     0



;* ************************************************************************ **
;*
;*
;* XRAM definitions
;*
;*
;*
;* ************************************************************************ */

        ; Define start address and length of extern RAM
        ; Used in startup.a51
        XDATASTART      EQU    0FC00H    ; the absolute start-address of XDATA memory
        XDATALEN        EQU     00400H   ; the length of XDATA memory in bytes.

;* ************************************************************************ **
;*
;*
;* Pins used for paging, etc.
;*
;*
;*
;* ************************************************************************ */



;* ************************************************************************ **
;*
;*
;* Macro for initializing control pins for external memory
;*
;*
;*
;* ************************************************************************ */

        ; This macro presets outputs for control of external memory.
        ; Used in startup.a51
        STARTUP_XMEM macro
        endm

;* ************************************************************************ **
;*
;*
;* xxx
;*
;*
;*
;* ************************************************************************ */