veriphy.h

Vitesse 24port gigabit Switch Source Code

/*

    Copyright (c) 2005 Vitesse Semiconductor Corporation "Vitesse".  
    All Rights Reserved.  Unpublished rights reserved under the copyright laws
    of the United States of America, other countries and international treaties.
    The software is provided without a fee. Permission to use, copy, store and 
    modify, the software and its source code is granted. Permission to integrate
    into other products, disclose, transmit and distribute the software in an
    absolute machine readable format (e.g. HEX file) is also granted. 

    The source code of the software may not be disclosed, transmitted or
    distributed without the written permission of Vitesse. The software and its
    source code may only be used in products utilizing a Vitesse VSC73xx product.
 
    This copyright notice must appear in any copy, modification, disclosure,
    transmission or distribution of the software. Vitesse retains all ownership,
    copyright, trade secret and proprietary rights in the software.  

    THIS SOFTWARE HAS BEEN PROVIDED "AS IS," WITHOUT EXPRESS OR IMPLIED WARRANTY
    INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR USE AND NON-INFRINGEMENT.

*/
#ifndef __VERIPHY_H__
#define __VERIPHY_H__

typedef struct {
    uchar state;
    uchar aux_delay;
    uchar ecAllZerosCount;
    uchar ecAllZerosCountPrev;
    uchar ecAllZerosAccum;
    uchar stat [4];     /* status for pairs A-D (0-3), 4-bit unsigned number, see below */
    uchar loc [4];      /* length/fault location for pairs A-D (0-3), 8-bit unsgn */
    short strength [4]; /* fault strength for pairs A-D (0-3), 14-bit signed int. */
    short log2VGAx256;  /* log2(VGA gain scalefactor)*256 (0 for link-down case) */ 
    short thresh[2];
    signed char signFlip;
    uchar flags;
    uchar media_sel_save;
} veriphy_parms_t;


void veriphy_start (uchar port_no, veriphy_parms_t *veriphy_parms_ptr);
uchar veriphy_run (uchar port_no, veriphy_parms_t *veriphy_parms_ptr);
void veriphy_done (uchar port_no, veriphy_parms_t *veriphy_parms_ptr);

/*
** The byte returned by veriphy_run indicates to the caller whether the cable 
** test has completed or veriphy_run has to be called again. If the test
** has completed, bit 7 is 1 and the remaining bits give the result.
** If the test has not completed, bit 7 is 0 and the remaining bits specify
** in 10 msec granularity how long time the caller must wait before calling 
** veriphy_run again.
*/
#define VERIPHY_CONTINUE          0
#define VERIPHY_WAIT_10_MSEC      1
#define VERIPHY_WAIT_200_MSEC    20
#define VERIPHY_WAIT_500_MSEC    50
#define VERIPHY_WAIT_750_MSEC    75

#define VERIPHY_DONE_MASK      0x80
#define VERIPHY_DONE_OK        (VERIPHY_DONE_MASK + 0)
#define VERIPHY_DONE_ANOMALY   (VERIPHY_DONE_MASK + 1)
#define VERIPHY_DONE_UNPLUGGED (VERIPHY_DONE_MASK + 2)

#endif