phydrv.h

Vitesse 24port gigabit Switch Source Code

/*

    Copyright (c) 2002-2005 Vitesse Semiconductor Corporation "Vitesse".  
    All Rights Reserved.  Unpublished rights reserved under the copyright laws
    of the United States of America, other countries and international treaties.
    The software is provided without a fee. Permission to use, copy, store and 
    modify, the software and its source code is granted. Permission to integrate
    into other products, disclose, transmit and distribute the software in an
    absolute machine readable format (e.g. HEX file) is also granted. 

    The source code of the software may not be disclosed, transmitted or
    distributed without the written permission of Vitesse. The software and its
    source code may only be used in products utilizing a Vitesse VSC73xx product.
 
    This copyright notice must appear in any copy, modification, disclosure,
    transmission or distribution of the software. Vitesse retains all ownership,
    copyright, trade secret and proprietary rights in the software.  

    THIS SOFTWARE HAS BEEN PROVIDED "AS IS," WITHOUT EXPRESS OR IMPLIED WARRANTY
    INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR USE AND NON-INFRINGEMENT.

*/
#ifndef __PHYDRV_H__
#define __PHYDRV_H__

typedef enum {
    PHY_VENDOR_UNKNOWN,
    PHY_VENDOR_VTSS,
} phy_vendor_t;

typedef enum {
    PHY_FAMILY_UNKNOWN,
    PHY_FAMILY_VTSS_8201,
    PHY_FAMILY_VTSS_8204,
    PHY_FAMILY_VTSS_8224,
    PHY_FAMILY_VTSS_8538,
    PHY_FAMILY_VTSS_7388,
    PHY_FAMILY_VTSS_7398,
    PHY_FAMILY_VTSS_7390,

} phy_family_t;

typedef enum {
    PHY_MODEL_UNKNOWN,
    PHY_MODEL_VTSS_8201,
    PHY_MODEL_VTSS_8204,
    PHY_MODEL_VTSS_8224,
    PHY_MODEL_VTSS_8234,
    PHY_MODEL_VTSS_8244,
    PHY_MODEL_VTSS_8538,
    PHY_MODEL_VTSS_8558,
    PHY_MODEL_VTSS_7388,
    PHY_MODEL_VTSS_7398,
    PHY_MODEL_VTSS_7390,
    PHY_MODEL_VTSS_7389,
    PHY_MODEL_VTSS_7391,

} phy_model_t;

typedef struct {
    phy_vendor_t vendor;
    phy_family_t family;
    phy_model_t  model; /* unique software id used by SW, *not* the same as model number */
    uchar        revision;
} phy_id_t;

ushort phy_read (uchar port_no, uchar reg_no) small;
void   phy_write (uchar port_no, uchar reg_no, ushort value) small;
void   phy_write_masked (uchar port_no, uchar reg_no, ushort value, ushort mask) small;
void   phy_read_id (uchar port_no, phy_id_t *phy_id_p);
void   phy_restart_aneg (uchar port_no);
void   phy_set_forced_speed (uchar port_no, uchar link_mode);
void   phy_reset (uchar port_no);
void   phy_post_reset (uchar port_no);
void   phy_immediate_init_seq_8538 (uchar port_no);
bool   phy_link_status (uchar port_no) small;
void phy_do_link_up_settings (uchar port_no, uchar link_mode);
void phy_do_link_down_settings (uchar port_no);
#if TRANSIT_VERIPHY
void phy_write_led_mode_reg (uchar port_no, ushort reg_value);
#endif /* TRANSIT_VERIPHY */

void phy_poll_sfp (void);
uchar phy_sfp_present (uchar port_no);

uchar sgmii_tr_read (uchar port_no, uchar reg_no);
void sgmii_tr_write (uchar port_no, uchar reg_no, uchar value);
void sgmii_lock_seq(uchar port_no);

void   phy_page_ext (uchar port_no);
void   phy_page_tr (uchar port_no);
void   phy_page_tp (uchar port_no);
void   phy_page_std (uchar port_no);

#if TRANSIT_VERIPHY

extern uchar data tr_raw_data [3];

void   phy_write_ext (uchar port_no, uchar reg, ushort val);
ushort phy_read_ext (uchar port_no, uchar reg);
void   phy_write_tr (uchar port_no, ushort ctrl_word);
void   phy_read_tr (uchar port_no, ushort ctrl_word);
void   phy_write_tp_bit (uchar port_no, uchar tp_reg_no, uchar bit_no, uchar bit_val);


#endif
#endif