tsc2101regs.h

cayman提供的PXA270 wince下的bsp源码包

#define CELLAGC_AGCTC_8_200		0x0008
#define CELLAGC_AGCTC_11_200	0x000a
#define CELLAGC_AGCTC_16_200	0x000c
#define CELLAGC_AGCTC_20_200	0x000e
#define CELLAGC_AGCTC_8_400		0x0010
#define CELLAGC_AGCTC_11_400	0x0012
#define CELLAGC_AGCTC_16_400	0x0014
#define CELLAGC_AGCTC_20_400	0x0016
#define CELLAGC_AGCTC_8_500		0x0018
#define CELLAGC_AGCTC_11_500	0x001a
#define CELLAGC_AGCTC_16_500	0x001c
#define CELLAGC_AGCTC_20_500	0x001e

// AGC enable for cell input
#define CELLAGC_AGCEN_OFF		0x0000
#define CELLAGC_AGCEN_ON		0x0001

// Driver power down status: TSC2101_DRVPD
// Delta-sigma scheme for DAC pop reduction
#define DRVPD_DPOPR_ENABLE		0x0200

// Clock rate for DAC pop reduction
#define DRVPD_CRATE_128			0x0000
#define DRVPD_CRATE_64			0x0100

// Duration for DAC pop reduction
#define DRVPD_DPTIME_14			0x0000
#define DRVPD_DPTIME_12			0x0040
#define DRVPD_DPTIME_10			0x0080
#define DRVPD_DPTIME_8			0x00c0

// disable driver pop sequencing
#define DRVPD_PSEQ_ENABLE		0x0000
#define DRVPD_PSEQ_DISABLE		0x0020

// Pop sequencing duration in cap mode
#define DRVPD_PSTIME_802		0x0000
#define DRVPD_PSTIME_4006		0x0010

// MIC AGC Control: TSC2101_MICAGC
// MAX PGA Value for Headset/Aux or Handset AGC
#define MICAGC_MMPGA_MASK		0xfe00

// De-bounce time for normal to silence mode
#define MICAGC_MDEBNS_0			0x0000
#define MICAGC_MDEBNS_0_5		0x0040
#define MICAGC_MDEBNS_1			0x0080
#define MICAGC_MDEBNS_2			0x00c0
#define MICAGC_MDEBNS_4			0x0100
#define MICAGC_MDEBNS_8			0x0140
#define MICAGC_MDEBNS_16		0x0180
#define MICAGC_MDEBNS_32		0x01c0

// De-bounce time for silence to normal mode
#define MICAGC_MDEBSN_0			0x0000
#define MICAGC_MDEBSN_0_5		0x0008
#define MICAGC_MDEBSN_1			0x0010
#define MICAGC_MDEBSN_2			0x0018
#define MICAGC_MDEBSN_4			0x0020
#define MICAGC_MDEBSN_8			0x0028
#define MICAGC_MDEBSN_16		0x0030
#define MICAGC_MDEBSN_32		0x0038

// Cell phone AGC control: TSC2101_CELLAGC2
// Max cell phone input PGA value
#define CELLAGC2_CMPGA_MASK		0xfe00

// De-bounce time for normal to silence mode
#define CELLAGC2_CDEBNS_0		0x0000
#define CELLAGC2_CDEBNS_0_5		0x0040
#define CELLAGC2_CDEBNS_1		0x0080
#define CELLAGC2_CDEBNS_2		0x00c0
#define CELLAGC2_CDEBNS_4		0x0100
#define CELLAGC2_CDEBNS_8		0x0140
#define CELLAGC2_CDEBNS_16		0x0180
#define CELLAGC2_CDEBNS_32		0x01c0

// De-bounce time for silence to normal mode
#define CELLAGC2_CDEBSN_0		0x0000
#define CELLAGC2_CDEBSN_0_5		0x0008
#define CELLAGC2_CDEBSN_1		0x0010
#define CELLAGC2_CDEBSN_2		0x0018
#define CELLAGC2_CDEBSN_4		0x0020
#define CELLAGC2_CDEBSN_8		0x0028
#define CELLAGC2_CDEBSN_16		0x0030
#define CELLAGC2_CDEBSN_32		0x0038




//**************************************************************
//
//			TSC2101 Initialization Value Definitions
//
//***************************************************************

// Values for Initalling TSC2101 Touch Screen Function
#define ADC_STOP_CONVERSIONS	(ADC_PSM_TSC | \
								 ADC_STS_STOP | \
								 ADC_AD_XY_SCAN | \
								 ADC_RS_12 | \
								 ADC_AV_4 | \
								 ADC_CL_1MHz | \
								 ADC_PV_100mS | \
                                 ADC_AVG_MEDIAN)
#define ADC_SETUP_VALUE_0		(ADC_PSM_HOST | \
								 ADC_STS_NORMAL | \
								 ADC_AD_XY_SCAN | \
								 ADC_RS_12 | \
								 ADC_AV_16 | \
								 ADC_CL_1MHz | \
								 ADC_PV_100mS | \
                                 ADC_AVG_MEDIAN)
#define ADC_SETUP_VALUE			(ADC_PSM_HOST | \
								 ADC_STS_STOP | \
								 ADC_AD_NOSCAN | \
								 ADC_RS_10 | \
								 ADC_AV_4 | \
								 ADC_CL_1MHz | \
								 ADC_PV_5mS | \
                                 ADC_AVG_MEDIAN)
#define ADC_XYSCAN_VALUE		(ADC_PSM_TSC | \
								 ADC_STS_NORMAL | \
								 ADC_AD_XY_SCAN | \
								 ADC_RS_10 | \
								 ADC_AV_4 | \
								 ADC_CL_4MHz | \
								 ADC_PV_1mS | \
                                 ADC_AVG_MEDIAN)

#define ADC_XYZSCAN_VALUE		(ADC_PSM_TSC | \
								 ADC_STS_NORMAL | \
								 ADC_AD_XYZ_SCAN | \
								 ADC_RS_12 | \
								 ADC_AV_4 | \
								 ADC_CL_2MHz | \
								 ADC_PV_1mS | \
                                 ADC_AVG_MEDIAN)

#define ADC_XSCAN_VALUE		(ADC_PSM_TSC | \
								 ADC_STS_NORMAL | \
								 ADC_AD_X_SCAN | \
								 ADC_RS_10 | \
								 ADC_AV_4 | \
								 ADC_CL_4MHz | \
								 ADC_PV_10mS | \
                                 ADC_AVG_MEDIAN)


#define ADC_YSCAN_VALUE		(ADC_PSM_TSC | \
								 ADC_STS_NORMAL | \
								 ADC_AD_Y_SCAN | \
								 ADC_RS_10 | \
								 ADC_AV_4 | \
								 ADC_CL_4MHz | \
								 ADC_PV_10mS | \
                                 ADC_AVG_MEDIAN)
                                 
#define ADC_BAT_VALUE			(ADC_PSM_HOST | \
								 ADC_STS_NORMAL | \
								 ADC_AD_BAT1_CONV | \
								 ADC_RS_12 | \
								 ADC_AV_4 | \
								 ADC_CL_1MHz | \
								 ADC_PV_1mS | \
                                 ADC_AVG_MEDIAN)
#define REF_SETUP_VALUE			(REF_INT_INTERNAL | REF_DL_1mS | \
								 REF_PDN_ON | REF_RFV_250)
#define CFG_SETUP_VALUE			(CFG_PRE_20 | CFG_SNS_32)

#define DELAY_SETUP_VALUE       (DELAY_NTS_EN | DELAY_NTS_112 | \
								 DELAY_TS_EN | DELAY_TS_10 | \
								 DELAY_CLK_INT | \
								 DELAY_CLKDIV_11)

// Values for Initalling TSC2101 GPIO Function
#define GPIO_SETUP_VALUE		(0)

// defines for TSC2101 default register values
//#define AUDCTL1_SETUP_VALUE		(AUDCTL1_ADCHPF_DISABLED | \
//								 AUDCTL1_WLEN_16 | \
//								 AUDCTL1_DATFM_I2S | \
//                                 AUDCTL1_DACFS_1 | \
//                                 AUDCTL1_ADCFS_1)
#define AUDCTL1_SETUP_VALUE		(AUDCTL1_ADCHPF_00125Fs | \
								 AUDCTL1_WLEN_16 | \
								 AUDCTL1_DATFM_I2S | \
                                 AUDCTL1_DACFS_1 | \
                                 AUDCTL1_ADCFS_1)
#define HEDVOL_SETUP_VALUE		(HEDVOL_ADMUT_MUTE | \
								 HEDVOL_AGCTG_05_5 | \
								 HEDVOL_AGCTC_8_100 | \
								 HEDVOL_AGCEN_OFF)
#define HEDVOL_SETUP_VALUE_VOICE 0x4000   //+32db
#define HEDVOL_SETUP_VALUE_MUTE  0x0000   //+0db
#define HEDVOL_SETUP_VALUE_AGC   0x7081   //0x7001   //+56db AGC for headset enable
#define HEDVOL_UNMUTE_VALUE		(HEDVOL_ADMUT_ACTIVE | \
								 HEDVOL_ADPGA_MASK | \
								 HEDVOL_AGCTG_05_5 | \
								 HEDVOL_AGCTC_8_100 | \
								 HEDVOL_AGCEN_OFF)
#define DACVOL_SETUP_VALUE		(DACVOL_DALMU_MUTE | \
                                 DACVOL_DARMU_MUTE)
#define DACVOL_SETUP_VALUE_VOICE		(DACVOL_DALMU_ACTIVE | \
                                 DACVOL_DARMU_ACTIVE)
//#define DACVOL_SETUP_VALUE_VOICE 0x4040   //DAC -32db
//#define DACVOL_SETUP_VALUE_VOICE 0x7F7F   //DAC -63.5db
#define MIXER_SETUP_VALUE		(MIXER_ASTMU_MUTE | \
                                 MIXER_MICSEL_SHND | \
								 MIXER_MICADC_MICSEL | \
								 MIXER_CPADC_NONE )
#define MIXER_SETUP_VALUE_SIDETONE 0x5F10
#define MIXER_SETUP_VALUE_VOICE  0xC510
#define MIXER_SETUP_VALUE_VOICE_HND  0xC530
#define AUDCTL2_SETUP_VALUE		(AUDCTL2_KCLEN_OFF | \
								 AUDCTL2_APGASS_ONE | \
								 AUDCTL2_DASTC_ONE)
#define AUDCTL2_SETUP_VALUE_VOICE 0xC410
#define AUDPD_SETUP_VALUE		(AUDPD_MBIAS_HND_OFF | \
								 AUDPD_MBIAS_HED_OFF | \
								 AUDPD_ASTPWD_OFF | \
								 AUDPD_SP1PWDN_OFF | \
								 AUDPD_SP2PWDN_OFF | \
								 AUDPD_DAPWDN_OFF | \
								 AUDPD_ADPWDN_OFF | \
								 AUDPD_VGPWDN_OFF | \
								 AUDPD_COPWDN_OFF | \
								 AUDPD_LSPWDN_OFF | \
								 AUDPD_BASSBCF_DISABLE | \
								 AUDPD_DEEMPF_DISABLE)
#define AUDPD_SETUP_VALUE_VOICE  0x21C4//0x21C7//0x21C4//0xE1C4//0xE1C7//0x20C7      //0x20c7 to disable out8 ,old 0x2087
#define AUDPD_SETUP_VALUE_OUT8   0x3887
#define AUDCTL3_SETUP_VALUE		(AUDCTL3_DMSVOL_INDEP | \
								 AUDCTL3_REFFS_44_1 | \
								 AUDCTL3_DAXFM_256S | \
								 AUDCTL3_SLVMS_SLAVE | \
								 AUDCTL3_CLPST_DISABLE)  //0x3004
#define AUDCTL3_SETUP_VALUE_AGC		(AUDCTL3_DMSVOL_INDEP | \
								 AUDCTL3_REFFS_44_1 | \
								 AUDCTL3_DAXFM_256S | \
								 AUDCTL3_SLVMS_SLAVE | \
								 AUDCTL3_CLPST_ENABLE)  //0x300C
#define PLL1_SETUP_VALUE		(PLL1_PLLSEL_DISABLE | \
								 (2 << 11) | \
								 (1 << 2))
#define PLL1_SETUP_VALUE_VOICE  0x9350
#define PLL2_SETUP_VALUE		(0)

// Using I2S/SYSCLK which is 11.343Mhz P=1,I=8,D=0 gives 44.3kHz.
// which is what the Intel processor is using for the sample rate.
#define PLL1_RUN_VALUE			(PLL1_PLLSEL_DISABLE | \
								 (2 << 11) | \
								 (1 << 8) | \
								 (8 << 2))
#define AUDCTL4_SETUP_VALUE		(AUDCTL4_ADSTPD_ENABLE | \
								 AUDCTL4_DASTPD_ENABLE | \
								 AUDCTL4_ASSTPD_ENABLE | \
								 AUDCTL4_CISTPD_DISABLE | \
								 AUDCTL4_BISTPD_DISABLE | \
								 AUDCTL4_AGCHYS_1 | \
								 AUDCTL4_MB_HED_3_3 | \
								 AUDCTL4_MB_HND_2_5)
#define AUDCTL4_SETUP_VALUE_VOICE		(AUDCTL4_ADSTPD_ENABLE | \
								 AUDCTL4_DASTPD_ENABLE | \
								 AUDCTL4_ASSTPD_ENABLE | \
								 AUDCTL4_CISTPD_DISABLE | \
								 AUDCTL4_BISTPD_DISABLE | \
								 AUDCTL4_AGCHYS_1 | \
								 AUDCTL4_MB_HED_2_0 | \
								 AUDCTL4_MB_HND_2_5)  //in order to detect headset
#define HNDVOL_SETUP_VALUE		(HNDVOL_ADMUT_MUTE | \
								 HNDVOL_AGCTG_05_5 | \
								 HNDVOL_AGCTC_8_100 | \
								 HNDVOL_AGCEN_OFF)
#define HNDVOL_SETUP_VALUE_VOICE 0x4000    //handset pga +32db
#define HNDVOL_SETUP_VALUE_AGC   0x7001   //handset pga and enable handset Input AGC
#define HNDVOL_UNMUTE_VALUE		(HNDVOL_ADMUT_ACTIVE | \
								 HNDVOL_ADPGA_MASK | \
								 HNDVOL_AGCTG_05_5 | \
								 HNDVOL_AGCTC_8_100 | \
								 HNDVOL_AGCEN_OFF)
#define CELLVOL_SETUP_VALUE		(CELLVOL_MUT_CP_MUTE | \
								 CELLVOL_MUT_BU_MUTE)
#define AUDCTL5_SETUP_VALUE		(AUDCTL5_DIFFIN_SINGLE | \
								 AUDCTL5_DAC2SPK1_LEFT | \
								 AUDCTL5_AST2SPK1_OFF | \
								 AUDCTL5_BUZ2SPK1_OFF | \
								 AUDCTL5_KCL2SPK1_OFF | \
								 AUDCTL5_CPI2SPK1_OFF | \
								 AUDCTL5_DAC2SPK2_RIGHT | \
								 AUDCTL5_AST2SPK2_OFF | \
								 AUDCTL5_BUZ2SPK2_OFF | \
								 AUDCTL5_KCL2SPK2_OFF | \
								 AUDCTL5_CPI2SPK2_OFF | \
								 AUDCTL5_MUTSPK1_ACTIVE | \
								 AUDCTL5_MUTSPK2_ACTIVE | \
								 AUDCTL5_HDSCPTC_ENABLE)
#define AUDCTL5_SETUP_VALUE_VOICE		(AUDCTL5_DIFFIN_SINGLE | \
								 AUDCTL5_DAC2SPK1_LEFT | \
								 AUDCTL5_AST2SPK1_OFF | \
								 AUDCTL5_BUZ2SPK1_OFF | \
								 AUDCTL5_KCL2SPK1_OFF | \
								 AUDCTL5_CPI2SPK1_OFF | \
								 AUDCTL5_DAC2SPK2_RIGHT | \
								 AUDCTL5_AST2SPK2_OFF | \
								 AUDCTL5_BUZ2SPK2_OFF | \
								 AUDCTL5_KCL2SPK2_OFF | \
								 AUDCTL5_CPI2SPK2_OFF | \
								 AUDCTL5_MUTSPK1_ACTIVE | \
								 AUDCTL5_MUTSPK2_ACTIVE | \
								 AUDCTL5_MUTSPK2_DISABLE)
#define AUDCTL5_SETUP_VALUE_SIDETONE		(AUDCTL5_DIFFIN_SINGLE | \
								 AUDCTL5_DAC2SPK1_LEFT | \
								 AUDCTL5_AST2SPK1_ON| \
								 AUDCTL5_BUZ2SPK1_OFF | \
								 AUDCTL5_KCL2SPK1_OFF | \
								 AUDCTL5_CPI2SPK1_OFF | \
								 AUDCTL5_DAC2SPK2_RIGHT | \
								 AUDCTL5_AST2SPK2_ON | \
								 AUDCTL5_BUZ2SPK2_OFF | \
								 AUDCTL5_KCL2SPK2_OFF | \
								 AUDCTL5_CPI2SPK2_OFF | \
								 AUDCTL5_MUTSPK1_ACTIVE | \
								 AUDCTL5_MUTSPK2_ACTIVE | \
								 AUDCTL5_HDSCPTC_ENABLE)
#define AUDCTL6_SETUP_VALUE		(AUDCTL6_SPL2LSK_OFF | \
								 AUDCTL6_AST2LSK_OFF | \
								 AUDCTL6_BUZ2LSK_OFF | \
								 AUDCTL6_KCL2LSK_OFF | \
								 AUDCTL6_CPI2LSK_OFF | \
								 AUDCTL6_MIC2CPO_OFF | \
								 AUDCTL6_SPL2CPO_OFF | \
								 AUDCTL6_SPR2CPO_OFF | \
								 AUDCTL6_MUTLSPK_MUTE | \
								 AUDCTL6_MUTSPK2_MUTE | \
								 AUDCTL6_LDSCPTC_ENABLE | \
								 AUDCTL6_VGNDSCPTC_ENABLE | \
								 AUDCTL6_CAPINTF_CAP)
#define AUDCTL6_SETUP_VALUE_OUT8		(AUDCTL6_SPL2LSK_ON | \
								 AUDCTL6_AST2LSK_OFF | \
								 AUDCTL6_BUZ2LSK_OFF | \
								 AUDCTL6_KCL2LSK_OFF | \
								 AUDCTL6_CPI2LSK_OFF | \
								 AUDCTL6_MIC2CPO_OFF | \
								 AUDCTL6_SPL2CPO_OFF | \
								 AUDCTL6_SPR2CPO_OFF | \
								 AUDCTL6_MUTLSPK_ACTIVE| \
								 AUDCTL6_MUTSPK2_MUTE | \
								 AUDCTL6_LDSCPTC_ENABLE | \
								 AUDCTL6_VGNDSCPTC_ENABLE | \
								 AUDCTL6_CAPINTF_CAPLESS)
#define AUDCTL7_SETUP_VALUE		(AUDCTL7_DETECT_DISABLE | \
								 AUDCTL7_HDDEBNPG_16 | \
								 AUDCTL7_BDEBNPG_0 | \
								 AUDCTL7_DGPIO2_DISABLE | \
								 AUDCTL7_DGPIO1_DISABLE | \
								 AUDCTL7_CLKGPIO2_DISABLE | \
								 AUDCTL7_ADWSF_TRI)
#define AUDCTL7_SETUP_VALUE_VOICE (AUDCTL7_DETECT_ENABLE| \
								 AUDCTL7_HDDEBNPG_16 | \
								 AUDCTL7_BDEBNPG_0 | \
								 AUDCTL7_DGPIO2_DISABLE | \
								 AUDCTL7_DGPIO1_DISABLE | \
								 AUDCTL7_CLKGPIO2_DISABLE | \
								 AUDCTL7_ADWSF_TRI)
#define CELLAGC_SETUP_VALUE		(CELLAGC_AGCNL_60| \
								 CELLAGC_AGCHYS_1 | \
								 CELLAGC_CLPST_DISABLE | \
								 CELLAGC_AGCTG_5_5 | \
								 CELLAGC_AGCTC_8_100 | \
								 CELLAGC_AGCEN_OFF)
#define DRVPD_SETUP_VALUE		(DRVPD_DPOPR_ENABLE | \
								 DRVPD_CRATE_128 | \
								 DRVPD_DPTIME_14 | \
								 DRVPD_PSEQ_ENABLE | \
								 DRVPD_PSTIME_802)
#define MICAGC_SETUP_VALUE		(MICAGC_MDEBNS_0 | \
								 MICAGC_MDEBSN_0)
#define MICAGC_SETUP_AGC		0xE048
#define CELLAGC2_SETUP_VALUE	(CELLAGC2_CDEBNS_0 | \
								 CELLAGC2_CDEBSN_0)
				


#endif

///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////