xscalesspcomm.h

cayman提供的PXA270 wince下的bsp源码包

/*************************************************************/
//
// Copyright (c) Texas Instruments 2003.  All rights reserved.
//
/**************************************************************
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT
LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR 
FITNESS FOR A PARTICULAR PURPOSE.

Module Name:	
		XscaleSSPComm.H

Abstract:	
		This header file contains the functions to setup 
		the Intel Xscale processor's PENIRQ interrupt to 
		interface with the /DAV of TI's TSC2101 device. 
		This is an example for using the interrupt of a
		host processor with TI's TSC2101 Windows CE. Net
		touch screen driver.

Functions:
  
Revision History:

***************************************************************/

#ifndef __XscaleSSPComm_H__
#define __XscaleSSPComm_H__

//
// Intel PXA250 (Xscale) Processor Registers
// Defines for SSP(SPI) Configuration
//
// defines for SSP Control Register 0 (SSCR0)
#define SSE_DISABLE	0x00
#define SSE_ENABLE	0x80

#define ECS_INTERNAL	0x00
#define ECS_EXTERNAL	0x40

#define FRF_MICROWIRE	0x20
#define FRF_TI			0x10
#define FRF_MOTOROLA	0x00

#define DSS_16_BIT		0x0F

#define SCR_1800_KHZ	0x0000	// Really	1.8432 Mbps
#define SCR_900_KHZ		0x0100	// Really	921.6 KHz
#define SCR_600_KHZ		0x0200	//			614.4 
#define SCR_300_KHZ		0x0400	//			368.64
#define SCR_200_KHZ		0x0800	//			204.8
#define SCR_100_KHZ		0x1100	//			102.4
#define SCR_50_KHZ		0x2300	//			51.2
#define SCR_7_KHZ		0xFF00  //			7.2

//add by liudiping 2004-11-12
#define SSCR0_SCR_KHZ   (0x15<<8)
#define SSCR0_SSP_EN	0x80

//add by liudiping 2004-11-12//
#define XLLP_BIT_17   ( 1u << 17 )
#define XLLP_BIT_18   ( 1u << 18 )
#define XLLP_BIT_19   ( 1u << 19 )
#define XLLP_BIT_20   ( 1u << 20 )

//by liudiping 2004-11-12
/* Pin  81-84  alternate functions */
#define XLLP_GPIO_AF_BIT_SSPTXD3            (0x01u << 2 )
#define XLLP_GPIO_AF_BIT_SSPRXD3            (0x01u << 4 )
#define XLLP_GPIO_AF_BIT_SSPSFRM3          (0x01u << 6 )
#define XLLP_GPIO_AF_BIT_SSPSCLK3           (0x01u  << 8)

// defines for SSP Control Register 1 (SSCR1)
#define RIE_DISABLE		0x00
#define RIE_ENABLE		0x01

#define TIE_DISABLE		0x00
#define TIE_ENABLE		0x02

#define LBM_DISABLE		0x00
#define LBM_ENABLE		0x40

#define SPO_IDLE_LOW	0x00
#define SPO_IDLE_HIGH	0x80

#define SPH_FULL_DELAY	0x00
#define SPH_HALF_DELAY	0x10

#define MWDS_8_BIT		0x00
#define MWDS_16_BIT		0x20

#define TFT_ZERO		0x0000
#define TFT_SEVEN		0x01C0

#define RFT_SEVEN		0x1C00
#define RFT_FIFTEEN		0x3C00

// defines for SSP Status Register (SSR)
#define TNF_FULL		0x00
#define TNF_NOT_FULL	0x02

#define RNE_EMPTY		0x00
#define RNE_NOT_EMPTY	0x40

#define BSY_IDLE		0x00
#define BSY_BUSY		0x80

#define TFS_NORMAL		0x00
#define TFS_IRQ_THROWN	0x10

#define RFS_NORMAL		0x00
#define RFS_IRQ_THROWN	0x20

#define ROR_NORMAL		0x00
#define ROR__OVERRUN	0x40

#define SPR_SHARE_COM4	0
#define SPR_USE_GPIO	1

#define GAFR_NORMAL		0
#define GAFR_ALTERNATE	1

#define GPDR_INPUT		0
#define GPDR_OUTPUT		1

// functions for SSP setup and configuration
BOOL HWInitializeSPIDriver(void);
void HWDeinitializeSPIDriver(void);
void HWSetupSPIController(BOOL InPowerHandle);
void HWStopSPIController(BOOL InPowerHandle);
void HWStartFrame(void);
void HWStopFrame(void);
void HWSPIWriteWord(unsigned __int16 *iWord);
unsigned __int16 HWSPIReadWord(void);
BOOL HWSPITxBusy(void);
BOOL HWSPIRxBusy(void);
BOOL HWSPIRXFIFONotEmpty(void);
void TXFIFOEntry(void);
BOOL HWSPITXFIFONotEmpty(void);
void HWSPIWait(unsigned int microSec);
BOOL HWIsTSC2101AlreadyReset(void);
void HWResetTSC2101(void);
#endif

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