reg66x.h

这项工程将让您把自己的MP3播放器平台

#ifndef _reg66x_h_
#define _reg66x_h_

// Revision history
// 30-May-05	RLA	Correct definition of TF2 (the 89C66x is non-standard
//			 in this regard.
// 		RLA	Add the mnemonics for interrupt vectors because, yes,
//			 the Philips parts are non-standard in some of the
//			 vectors (e.g. timer 2)!!
//			Add mnemonics for the SMOD bits because, yes again, the
//			 Philips parts are non-standard!

// Ditto for SDCC...
#define SFR(NAME,ADDRESS) sfr at ADDRESS NAME
#define SBIT(NAME,REGISTER,BIT) sbit at REGISTER+BIT NAME

// Standard registers (PSW, ACC, B, DPH/DPL, SP, etc)...
SFR(SP, 0x81);
SFR(DPL, 0x82);
SFR(DPH, 0x83);
SFR(PSW, 0xD0);
  SBIT(CY,  0xD0, 7);
  SBIT(AC,  0xD0, 6);
  SBIT(F0,  0xD0, 5);
  SBIT(RS1, 0xD0, 4);
  SBIT(RS0, 0xD0, 3);
  SBIT(OV,  0xD0, 2);
  SBIT(UD,  0xD0, 1);
  SBIT(P,   0xD0, 0);
SFR(ACC, 0xE0);
  SBIT(ACC7, 0xE0, 7);
  SBIT(ACC6, 0xE0, 6);
  SBIT(ACC5, 0xE0, 5);
  SBIT(ACC4, 0xE0, 4);
  SBIT(ACC3, 0xE0, 3);
  SBIT(ACC2, 0xE0, 2);
  SBIT(ACC1, 0xE0, 1);
  SBIT(ACC0, 0xE0, 0);
SFR(B, 0xF0);


// I/O Ports...
SFR(P0, 0x80);
  SBIT(P0_7, 0x80, 7);
  SBIT(P0_6, 0x80, 6);
  SBIT(P0_5, 0x80, 5);
  SBIT(P0_4, 0x80, 4);
  SBIT(P0_3, 0x80, 3);
  SBIT(P0_2, 0x80, 2);
  SBIT(P0_1, 0x80, 1);
  SBIT(P0_0, 0x80, 0);
SFR(P1, 0x90);
  SBIT(P1_7, 0x90, 7);
  SBIT(P1_6, 0x90, 6);
  SBIT(P1_5, 0x90, 5);
  SBIT(P1_4, 0x90, 4);
  SBIT(P1_3, 0x90, 3);
  SBIT(P1_2, 0x90, 2);
  SBIT(P1_1, 0x90, 1);
  SBIT(P1_0, 0x90, 0);
SFR(P2, 0xA0);
  SBIT(P2_7, 0xA0, 7);
  SBIT(P2_6, 0xA0, 6);
  SBIT(P2_5, 0xA0, 5);
  SBIT(P2_4, 0xA0, 4);
  SBIT(P2_3, 0xA0, 3);
  SBIT(P2_2, 0xA0, 2);
  SBIT(P2_1, 0xA0, 1);
  SBIT(P2_0, 0xA0, 0);
SFR(P3, 0xB0);
  SBIT(P3_7, 0xB0, 7);
  SBIT(P3_6, 0xB0, 6);
  SBIT(P3_5, 0xB0, 5);
  SBIT(P3_4, 0xB0, 4);
  SBIT(P3_3, 0xB0, 3);
  SBIT(P3_2, 0xB0, 2);
  SBIT(P3_1, 0xB0, 1);
  SBIT(P3_0, 0xB0, 0);

// Synonyms for some of the dual-function I/O pins...  
#define T2	P1_0
#define T2EX	P1_1
#define ECI	P1_2
#define CEX0	P1_3
#define CEX1	P1_4
#define CEX2	P1_5
#define SCL	P1_6
#define SDA	P1_7
#define RXD	P3_0
#define TXD	P3_1
#define INT0	P3_2
#define INT1	P3_3
#define T0	P3_4
#define T1	P3_5
#define WR	P3_6
#define RD	P3_7


// Timer 0 and 1 registers and bits...
SFR(TCON, 0x88);
  SBIT(TF1, 0x88, 7);
  SBIT(TR1, 0x88, 6);
  SBIT(TF0, 0x88, 5);
  SBIT(TR0, 0x88, 4);
  SBIT(IE1, 0x88, 3);
  SBIT(IT1, 0x88, 2);
  SBIT(IE0, 0x88, 1);
  SBIT(IT0, 0x88, 0);
SFR(TMOD, 0x89);
SFR(TL0, 0x8A);
SFR(TL1, 0x8B);
SFR(TH0, 0x8C);
SFR(TH1, 0x8D);

// Timer 2 registers...
SFR(T2CON, 0xC8);
  SBIT(TF2,   0xC8, 7);
  SBIT(EXF2,  0xC8, 6);
  SBIT(RCLK,  0xC8, 5);
  SBIT(TCLK,  0xC8, 4);
  SBIT(EXEN2, 0xC8, 3);
  SBIT(TR2,   0xC8, 2);
  SBIT(CT2,   0xC8, 1);
  SBIT(CPRL2, 0xC8, 0);
SFR(T2MOD, 0xC9);
SFR(RCAP2L, 0xCA);
SFR(RCAP2H, 0xCB);
SFR(TL2, 0xCC);
SFR(TH2, 0xCD);


// Serial port 0 (the traditional 8051 serial port)...
SFR(S0CON, 0x98);
  SBIT(SM0, 0x98, 7);
  SBIT(FE,  0x98, 7);
  SBIT(SM1, 0x98, 6);
  SBIT(SM2, 0x98, 5);
  SBIT(REN, 0x98, 4);
  SBIT(TB8, 0x98, 3);
  SBIT(RB8, 0x98, 2);
  SBIT(TI,  0x98, 1);
  SBIT(RI,  0x98, 0);
SFR(S0BUF, 0x99);
#define SCON S0CON
#define SBUF S0BUF

// Serial port 1 (the I2C port)...
SFR(SADDR, 0xA9);
SFR(SADEN, 0xB9);
SFR(S1CON, 0xD8);
  SBIT(CR2,  0xD8, 7);
  SBIT(ENS1, 0xD8, 6);
  SBIT(STA,  0xD8, 5);
  SBIT(STO,  0xD8, 4);
  SBIT(SI,   0xD8, 3);
  SBIT(AA,   0xD8, 2);
  SBIT(CR1,  0xD8, 1);
  SBIT(CR0,  0xD8, 0);
SFR(S1STA, 0xD9);
SFR(S1DAT, 0xDA);
SFR(S1ADR, 0xDB);
SFR(S1IST, 0xDC);


// Interrupt enable registers (the 89C66x has two)...
SFR(IEN0, 0xA8);
  SBIT(EA,  0xA8, 7);
  SBIT(EC,  0xA8, 6);
  SBIT(ES1, 0xA8, 5);
  SBIT(ES0, 0xA8, 4);
  SBIT(ET1, 0xA8, 3);
  SBIT(EX1, 0xA8, 2);
  SBIT(ET0, 0xA8, 1);
  SBIT(EX0, 0xA8, 0);
#define IE IEN0
SFR(IEN1, 0xE8);
  SBIT(ET2, 0xE8, 0);

// Interrupt priority registers...
SFR(IPH, 0xB7);
#define PT2H	0x80
#define PPCH	0x40
#define PS1H	0x20
#define PS0H	0x10
#define PT1H	0x08
#define PX1H	0x04
#define PT0H	0x02
#define PX0H	0x01
SFR(IP, 0xB8);
  SBIT(PT2, 0xB8, 7);
  SBIT(PPC, 0xB8, 6);
  SBIT(PS1, 0xB8, 5);
  SBIT(PS0, 0xB8, 4);
  SBIT(PT1, 0xB8, 3);
  SBIT(PX1, 0xB8, 2);
  SBIT(PT0, 0xB8, 1);
  SBIT(PX0, 0xB8, 0);


// PCON (Power Control) register...
SFR(PCON, 0x87);
#define SMOD1	0x80
#define SMOD0	0x40
#define SMOD	SMOD0
#define POF	0x10
#define GF1	0x08
#define GF0	0x04
#define PD	0x02
#define IDL	0x01


// "Auxiliary" registers ...
//  (you'd think Philips could have come up with a better name!)
SFR(AUXR, 0x8E);
#define EXTRAM	0x02
#define AO	0x01
SFR(AUXR1, 0xA2);
#define ENBOOT	0x20
#define GF2	0x08
#define DPS	0x01


// Programmable Counter Array (PCA) registers...
SFR(CCON, 0xC0);
  SBIT(CF,   0xC0, 7);
  SBIT(CR,   0xC0, 6);
  SBIT(CCF4, 0xC0, 4);
  SBIT(CCF3, 0xC0, 3);
  SBIT(CCF2, 0xC0, 2);
  SBIT(CCF1, 0xC0, 1);
  SBIT(CCF0, 0xC0, 0);
SFR(CMOD, 0xC1);
#define CIDL	0x80
#define WDTE	0x40
#define CPS1	0x04
#define CPS0	0x02
#define ECF	0x01
SFR(CCAPM0, 0xC2);
#define ECOM	0x40
#define CAPP	0x20
#define CAPN	0x10
#define MAT	0x08
#define TOG	0x04
#define PWM	0x02
#define ECCF	0x01
SFR(CCAPM1, 0xC3);
SFR(CCAPM2, 0xC4);
SFR(CCAPM3, 0xC5);
SFR(CCAPM4, 0xC6);
SFR(CL, 0xE9);
SFR(CCAP0L, 0xEA);
SFR(CCAP1L, 0xEB);
SFR(CCAP2L, 0xEC);
SFR(CCAP3L, 0xED);
SFR(CCAP4L, 0xEE);
SFR(CH, 0xF9);
SFR(CCAP0H, 0xFA);
SFR(CCAP1H, 0xFB);
SFR(CCAP2H, 0xFC);
SFR(CCAP3H, 0xFD);
SFR(CCAP4H, 0xFE);


// Watchdog timer reset...
SFR(WDTRST, 0xA6);

// Interrupt vectors.
#define INT0_VECTOR	0	// 00003H
#define TIMER0_VECTOR	1	// 0000BH
#define INT1_VECTOR	2	// 00013H
#define TIMER1_VECTOR	3	// 0001BH
#define SERIAL_VECTOR	4	// 00023H
#define I2C_VECTOR	5	// 0002BH
#define PCA_VECTOR	6	// 00033H
#define TIMER2_VECTOR	7	// 0003BH (NON-STANDARD!!)

#undef SBIT
#undef SFR
#endif	// ifndef _reg66x_