division.map.qmsg

使用C8051F020和FPGA等其它相关硬件制作的一个程控滤波器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 05 07:35:42 2007 " "Info: Processing started: Wed Sep 05 07:35:42 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off division -c division " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off division -c division" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "division.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file division.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 division-one " "Info: Found design unit 1: division-one" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 division " "Info: Found entity 1: division" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "division " "Info: Elaborating entity \"division\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pll.vhd 2 1 " "Warning: Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll-SYN " "Info: Found design unit 1: pll-SYN" {  } { { "pll.vhd" "" { Text "E:/滤波器/数控分频器FPGA/pll.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.vhd" "" { Text "E:/滤波器/数控分频器FPGA/pll.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll pll:u1 " "Info: Elaborating entity \"pll\" for hierarchy \"pll:u1\"" {  } { { "division.vhd" "u1" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 97 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 454 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll:u1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll:u1\|altpll:altpll_component\"" {  } { { "pll.vhd" "altpll_component" { Text "E:/滤波器/数控分频器FPGA/pll.vhd" 128 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pll:u1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"pll:u1\|altpll:altpll_component\"" {  } { { "pll.vhd" "" { Text "E:/滤波器/数控分频器FPGA/pll.vhd" 128 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|division\|s 10 " "Info: State machine \"\|division\|s\" contains 10 states" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|division\|s " "Info: Selected Auto state machine encoding method for state machine \"\|division\|s\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|division\|s " "Info: Encoding result for state machine \"\|division\|s\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "10 " "Info: Completed encoding using 10 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s9 " "Info: Encoded state bit \"s.s9\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s8 " "Info: Encoded state bit \"s.s8\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s7 " "Info: Encoded state bit \"s.s7\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s6 " "Info: Encoded state bit \"s.s6\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s5 " "Info: Encoded state bit \"s.s5\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s4 " "Info: Encoded state bit \"s.s4\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s3 " "Info: Encoded state bit \"s.s3\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s2 " "Info: Encoded state bit \"s.s2\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s1 " "Info: Encoded state bit \"s.s1\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "s.s0 " "Info: Encoded state bit \"s.s0\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s0 0000000000 " "Info: State \"\|division\|s.s0\" uses code string \"0000000000\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s1 0000000011 " "Info: State \"\|division\|s.s1\" uses code string \"0000000011\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s2 0000000101 " "Info: State \"\|division\|s.s2\" uses code string \"0000000101\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s3 0000001001 " "Info: State \"\|division\|s.s3\" uses code string \"0000001001\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s4 0000010001 " "Info: State \"\|division\|s.s4\" uses code string \"0000010001\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s5 0000100001 " "Info: State \"\|division\|s.s5\" uses code string \"0000100001\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s6 0001000001 " "Info: State \"\|division\|s.s6\" uses code string \"0001000001\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s7 0010000001 " "Info: State \"\|division\|s.s7\" uses code string \"0010000001\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s8 0100000001 " "Info: State \"\|division\|s.s8\" uses code string \"0100000001\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|division\|s.s9 1000000001 " "Info: State \"\|division\|s.s9\" uses code string \"1000000001\"" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "48 " "Info: Implemented 48 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "34 " "Info: Implemented 34 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 05 07:35:51 2007 " "Info: Processing ended: Wed Sep 05 07:35:51 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}