prev_cmp_division.tan.qmsg

使用C8051F020和FPGA等其它相关硬件制作的一个程控滤波器

{ "Info" "ITDB_TH_RESULT" "cnt4b\[1\] datab\[1\] clkin 0.740 ns register " "Info: th for register \"cnt4b\[1\]\" (data pin = \"datab\[1\]\", clock pin = \"clkin\") is 0.740 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 7.495 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to destination register is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk 2 REG LC_X8_Y10_N5 11 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y10_N5; Fanout = 11; REG Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clkin clk } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.491 ns) + CELL(0.711 ns) 7.495 ns cnt4b\[1\] 3 REG LC_X1_Y7_N4 3 " "Info: 3: + IC(3.491 ns) + CELL(0.711 ns) = 7.495 ns; Loc. = LC_X1_Y7_N4; Fanout = 3; REG Node = 'cnt4b\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { clk cnt4b[1] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.56 % ) " "Info: Total cell delay = 3.115 ns ( 41.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.380 ns ( 58.44 % ) " "Info: Total interconnect delay = 4.380 ns ( 58.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4b[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4b[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 47 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.770 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.770 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns datab\[1\] 1 PIN PIN_43 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_43; Fanout = 1; PIN Node = 'datab\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { datab[1] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.563 ns) + CELL(0.738 ns) 6.770 ns cnt4b\[1\] 2 REG LC_X1_Y7_N4 3 " "Info: 2: + IC(4.563 ns) + CELL(0.738 ns) = 6.770 ns; Loc. = LC_X1_Y7_N4; Fanout = 3; REG Node = 'cnt4b\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.301 ns" { datab[1] cnt4b[1] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 32.60 % ) " "Info: Total cell delay = 2.207 ns ( 32.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.563 ns ( 67.40 % ) " "Info: Total interconnect delay = 4.563 ns ( 67.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.770 ns" { datab[1] cnt4b[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.770 ns" { datab[1] datab[1]~out0 cnt4b[1] } { 0.000ns 0.000ns 4.563ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4b[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4b[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.770 ns" { datab[1] cnt4b[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.770 ns" { datab[1] datab[1]~out0 cnt4b[1] } { 0.000ns 0.000ns 4.563ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 26 09:10:17 2007 " "Info: Processing ended: Thu Jul 26 09:10:17 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}