prev_cmp_division.tan.qmsg

使用C8051F020和FPGA等其它相关硬件制作的一个程控滤波器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk " "Info: Detected ripple clock \"clk\" as buffer" {  } { { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 18 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clkin register register cnt4a\[1\] cnt4a\[1\] 275.03 MHz Internal " "Info: Clock \"clkin\" Internal fmax is restricted to 275.03 MHz between source register \"cnt4a\[1\]\" and destination register \"cnt4a\[1\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.092 ns + Longest register register " "Info: + Longest register to register delay is 2.092 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt4a\[1\] 1 REG LC_X1_Y5_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N0; Fanout = 3; REG Node = 'cnt4a\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4a[1] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.759 ns) + CELL(0.590 ns) 1.349 ns Equal0~18 2 COMB LC_X1_Y5_N6 3 " "Info: 2: + IC(0.759 ns) + CELL(0.590 ns) = 1.349 ns; Loc. = LC_X1_Y5_N6; Fanout = 3; COMB Node = 'Equal0~18'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.349 ns" { cnt4a[1] Equal0~18 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.434 ns) + CELL(0.309 ns) 2.092 ns cnt4a\[1\] 3 REG LC_X1_Y5_N0 3 " "Info: 3: + IC(0.434 ns) + CELL(0.309 ns) = 2.092 ns; Loc. = LC_X1_Y5_N0; Fanout = 3; REG Node = 'cnt4a\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.743 ns" { Equal0~18 cnt4a[1] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.899 ns ( 42.97 % ) " "Info: Total cell delay = 0.899 ns ( 42.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.193 ns ( 57.03 % ) " "Info: Total interconnect delay = 1.193 ns ( 57.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.092 ns" { cnt4a[1] Equal0~18 cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.092 ns" { cnt4a[1] Equal0~18 cnt4a[1] } { 0.000ns 0.759ns 0.434ns } { 0.000ns 0.590ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 7.495 ns + Shortest register " "Info: + Shortest clock path from clock \"clkin\" to destination register is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk 2 REG LC_X8_Y10_N5 11 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y10_N5; Fanout = 11; REG Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clkin clk } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.491 ns) + CELL(0.711 ns) 7.495 ns cnt4a\[1\] 3 REG LC_X1_Y5_N0 3 " "Info: 3: + IC(3.491 ns) + CELL(0.711 ns) = 7.495 ns; Loc. = LC_X1_Y5_N0; Fanout = 3; REG Node = 'cnt4a\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { clk cnt4a[1] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.56 % ) " "Info: Total cell delay = 3.115 ns ( 41.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.380 ns ( 58.44 % ) " "Info: Total interconnect delay = 4.380 ns ( 58.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 7.495 ns - Longest register " "Info: - Longest clock path from clock \"clkin\" to source register is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk 2 REG LC_X8_Y10_N5 11 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y10_N5; Fanout = 11; REG Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clkin clk } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.491 ns) + CELL(0.711 ns) 7.495 ns cnt4a\[1\] 3 REG LC_X1_Y5_N0 3 " "Info: 3: + IC(3.491 ns) + CELL(0.711 ns) = 7.495 ns; Loc. = LC_X1_Y5_N0; Fanout = 3; REG Node = 'cnt4a\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { clk cnt4a[1] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.56 % ) " "Info: Total cell delay = 3.115 ns ( 41.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.380 ns ( 58.44 % ) " "Info: Total interconnect delay = 4.380 ns ( 58.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.092 ns" { cnt4a[1] Equal0~18 cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.092 ns" { cnt4a[1] Equal0~18 cnt4a[1] } { 0.000ns 0.759ns 0.434ns } { 0.000ns 0.590ns 0.309ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[1] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4a[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { cnt4a[1] } {  } {  } "" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "cnt4a\[3\] dataa\[3\] clkin 0.129 ns register " "Info: tsu for register \"cnt4a\[3\]\" (data pin = \"dataa\[3\]\", clock pin = \"clkin\") is 0.129 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.587 ns + Longest pin register " "Info: + Longest pin to register delay is 7.587 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns dataa\[3\] 1 PIN PIN_45 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_45; Fanout = 1; PIN Node = 'dataa\[3\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { dataa[3] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.380 ns) + CELL(0.738 ns) 7.587 ns cnt4a\[3\] 2 REG LC_X1_Y5_N3 3 " "Info: 2: + IC(5.380 ns) + CELL(0.738 ns) = 7.587 ns; Loc. = LC_X1_Y5_N3; Fanout = 3; REG Node = 'cnt4a\[3\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.118 ns" { dataa[3] cnt4a[3] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.207 ns ( 29.09 % ) " "Info: Total cell delay = 2.207 ns ( 29.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.380 ns ( 70.91 % ) " "Info: Total interconnect delay = 5.380 ns ( 70.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.587 ns" { dataa[3] cnt4a[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.587 ns" { dataa[3] dataa[3]~out0 cnt4a[3] } { 0.000ns 0.000ns 5.380ns } { 0.000ns 1.469ns 0.738ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin destination 7.495 ns - Shortest register " "Info: - Shortest clock path from clock \"clkin\" to destination register is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk 2 REG LC_X8_Y10_N5 11 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y10_N5; Fanout = 11; REG Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clkin clk } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.491 ns) + CELL(0.711 ns) 7.495 ns cnt4a\[3\] 3 REG LC_X1_Y5_N3 3 " "Info: 3: + IC(3.491 ns) + CELL(0.711 ns) = 7.495 ns; Loc. = LC_X1_Y5_N3; Fanout = 3; REG Node = 'cnt4a\[3\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { clk cnt4a[3] } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.56 % ) " "Info: Total cell delay = 3.115 ns ( 41.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.380 ns ( 58.44 % ) " "Info: Total interconnect delay = 4.380 ns ( 58.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[3] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.587 ns" { dataa[3] cnt4a[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.587 ns" { dataa[3] dataa[3]~out0 cnt4a[3] } { 0.000ns 0.000ns 5.380ns } { 0.000ns 1.469ns 0.738ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk cnt4a[3] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk cnt4a[3] } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkin freqa freqa~reg0 11.435 ns register " "Info: tco from clock \"clkin\" to destination pin \"freqa\" through register \"freqa~reg0\" is 11.435 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkin source 7.495 ns + Longest register " "Info: + Longest clock path from clock \"clkin\" to source register is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clkin 1 CLK PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 1; CLK Node = 'clkin'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clkin } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.935 ns) 3.293 ns clk 2 REG LC_X8_Y10_N5 11 " "Info: 2: + IC(0.889 ns) + CELL(0.935 ns) = 3.293 ns; Loc. = LC_X8_Y10_N5; Fanout = 11; REG Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clkin clk } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.491 ns) + CELL(0.711 ns) 7.495 ns freqa~reg0 3 REG LC_X1_Y5_N2 2 " "Info: 3: + IC(3.491 ns) + CELL(0.711 ns) = 7.495 ns; Loc. = LC_X1_Y5_N2; Fanout = 2; REG Node = 'freqa~reg0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.202 ns" { clk freqa~reg0 } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 41.56 % ) " "Info: Total cell delay = 3.115 ns ( 41.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.380 ns ( 58.44 % ) " "Info: Total interconnect delay = 4.380 ns ( 58.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk freqa~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk freqa~reg0 } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.716 ns + Longest register pin " "Info: + Longest register to pin delay is 3.716 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freqa~reg0 1 REG LC_X1_Y5_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y5_N2; Fanout = 2; REG Node = 'freqa~reg0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { freqa~reg0 } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 34 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.592 ns) + CELL(2.124 ns) 3.716 ns freqa 2 PIN PIN_39 0 " "Info: 2: + IC(1.592 ns) + CELL(2.124 ns) = 3.716 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'freqa'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.716 ns" { freqa~reg0 freqa } "NODE_NAME" } } { "division.vhd" "" { Text "C:/Documents and Settings/YTB/桌面/division/division.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 57.16 % ) " "Info: Total cell delay = 2.124 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.592 ns ( 42.84 % ) " "Info: Total interconnect delay = 1.592 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.716 ns" { freqa~reg0 freqa } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.716 ns" { freqa~reg0 freqa } { 0.000ns 1.592ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { clkin clk freqa~reg0 } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { clkin clkin~out0 clk freqa~reg0 } { 0.000ns 0.000ns 0.889ns 3.491ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.716 ns" { freqa~reg0 freqa } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.716 ns" { freqa~reg0 freqa } { 0.000ns 1.592ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}