division.hier_info

使用C8051F020和FPGA等其它相关硬件制作的一个程控滤波器

|division
clk50M => pll:u1.inclk0
a_data[0] => dataa[0].DATAIN
a_data[1] => dataa[1].DATAIN
a_data[2] => dataa[2].DATAIN
a_data[3] => dataa[3].DATAIN
b_data[0] => datab[0].DATAIN
b_data[1] => datab[1].DATAIN
b_data[2] => datab[2].DATAIN
b_data[3] => datab[3].DATAIN
ena => freqa~1.OUTPUTSELECT
ena => freqb~1.OUTPUTSELECT
ena => cnt4b[1].ENA
ena => cnt4b[0].ENA
ena => cnt4b[2].ENA
ena => cnt4b[3].ENA
ena => cnt4a[0].ENA
ena => cnt4a[1].ENA
ena => cnt4a[2].ENA
ena => cnt4a[3].ENA
ena => datab[0].ENA
ena => datab[1].ENA
ena => datab[2].ENA
ena => datab[3].ENA
ena => dataa[0].ENA
ena => dataa[1].ENA
ena => dataa[2].ENA
ena => dataa[3].ENA
updata => datab[0].CLK
updata => datab[1].CLK
updata => datab[2].CLK
updata => datab[3].CLK
updata => dataa[0].CLK
updata => dataa[1].CLK
updata => dataa[2].CLK
updata => dataa[3].CLK
freqa <= freqa~reg0.DB_MAX_OUTPUT_PORT_TYPE
freqb <= freqb~reg0.DB_MAX_OUTPUT_PORT_TYPE


|division|pll:u1
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|division|pll:u1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
clk[0] <= clk[0]~0.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= <GND>
clk[2] <= <GND>
clk[3] <= <GND>
clk[4] <= <GND>
clk[5] <= <GND>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>