📄 division.tan.qmsg
字号:
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 register s.s6 register s.s7 861 ps " "Info: Minimum slack time is 861 ps for clock \"pll:u1\|altpll:altpll_component\|_clk0\" between source register \"s.s6\" and destination register \"s.s7\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.652 ns + Shortest register register " "Info: + Shortest register to register delay is 0.652 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s.s6 1 REG LC_X16_Y11_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N2; Fanout = 1; REG Node = 's.s6'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { s.s6 } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.537 ns) + CELL(0.115 ns) 0.652 ns s.s7 2 REG LC_X16_Y11_N4 1 " "Info: 2: + IC(0.537 ns) + CELL(0.115 ns) = 0.652 ns; Loc. = LC_X16_Y11_N4; Fanout = 1; REG Node = 's.s7'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.652 ns" { s.s6 s.s7 } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns ( 17.64 % ) " "Info: Total cell delay = 0.115 ns ( 17.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.537 ns ( 82.36 % ) " "Info: Total interconnect delay = 0.537 ns ( 82.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.652 ns" { s.s6 s.s7 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.652 ns" { s.s6 s.s7 } { 0.000ns 0.537ns } { 0.000ns 0.115ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:u1\|altpll:altpll_component\|_clk0 20.000 ns -1.885 ns 50 " "Info: Clock period of Destination clock \"pll:u1\|altpll:altpll_component\|_clk0\" is 20.000 ns with offset of -1.885 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:u1\|altpll:altpll_component\|_clk0 20.000 ns -1.885 ns 50 " "Info: Clock period of Source clock \"pll:u1\|altpll:altpll_component\|_clk0\" is 20.000 ns with offset of -1.885 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 destination 2.368 ns + Longest register " "Info: + Longest clock path from clock \"pll:u1\|altpll:altpll_component\|_clk0\" to destination register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 11; CLK Node = 'pll:u1\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.711 ns) 2.368 ns s.s7 2 REG LC_X16_Y11_N4 1 " "Info: 2: + IC(1.657 ns) + CELL(0.711 ns) = 2.368 ns; Loc. = LC_X16_Y11_N4; Fanout = 1; REG Node = 's.s7'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.03 % ) " "Info: Total cell delay = 0.711 ns ( 30.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.657 ns ( 69.97 % ) " "Info: Total interconnect delay = 1.657 ns ( 69.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 source 2.368 ns - Shortest register " "Info: - Shortest clock path from clock \"pll:u1\|altpll:altpll_component\|_clk0\" to source register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 11; CLK Node = 'pll:u1\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.711 ns) 2.368 ns s.s6 2 REG LC_X16_Y11_N2 1 " "Info: 2: + IC(1.657 ns) + CELL(0.711 ns) = 2.368 ns; Loc. = LC_X16_Y11_N2; Fanout = 1; REG Node = 's.s6'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.03 % ) " "Info: Total cell delay = 0.711 ns ( 30.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.657 ns ( 69.97 % ) " "Info: Total interconnect delay = 1.657 ns ( 69.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 27 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.652 ns" { s.s6 s.s7 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "0.652 ns" { s.s6 s.s7 } { 0.000ns 0.537ns } { 0.000ns 0.115ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s7 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { pll:u1|altpll:altpll_component|_clk0 s.s6 } { 0.000ns 1.657ns } { 0.000ns 0.711ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "cnt4b\[3\] ena clk50M 1.604 ns register " "Info: tsu for register \"cnt4b\[3\]\" (data pin = \"ena\", clock pin = \"clk50M\") is 1.604 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.490 ns + Longest pin register " "Info: + Longest pin to register delay is 7.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns ena 1 PIN PIN_39 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 18; PIN Node = 'ena'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { ena } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 10 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.154 ns) + CELL(0.867 ns) 7.490 ns cnt4b\[3\] 2 REG LC_X1_Y7_N2 3 " "Info: 2: + IC(5.154 ns) + CELL(0.867 ns) = 7.490 ns; Loc. = LC_X1_Y7_N2; Fanout = 3; REG Node = 'cnt4b\[3\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.021 ns" { ena cnt4b[3] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns ( 31.19 % ) " "Info: Total cell delay = 2.336 ns ( 31.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.154 ns ( 68.81 % ) " "Info: Total interconnect delay = 5.154 ns ( 68.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.490 ns" { ena cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.490 ns" { ena ena~out0 cnt4b[3] } { 0.000ns 0.000ns 5.154ns } { 0.000ns 1.469ns 0.867ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk50M pll:u1\|altpll:altpll_component\|_clk0 -1.885 ns - " "Info: - Offset between input clock \"clk50M\" and output clock \"pll:u1\|altpll:altpll_component\|_clk0\" is -1.885 ns" { } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 7 -1 0 } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 destination 7.808 ns - Shortest register " "Info: - Shortest clock path from clock \"pll:u1\|altpll:altpll_component\|_clk0\" to destination register is 7.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 11; CLK Node = 'pll:u1\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.935 ns) 2.592 ns clk 2 REG LC_X16_Y10_N0 10 " "Info: 2: + IC(1.657 ns) + CELL(0.935 ns) = 2.592 ns; Loc. = LC_X16_Y10_N0; Fanout = 10; REG Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.592 ns" { pll:u1|altpll:altpll_component|_clk0 clk } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.505 ns) + CELL(0.711 ns) 7.808 ns cnt4b\[3\] 3 REG LC_X1_Y7_N2 3 " "Info: 3: + IC(4.505 ns) + CELL(0.711 ns) = 7.808 ns; Loc. = LC_X1_Y7_N2; Fanout = 3; REG Node = 'cnt4b\[3\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.216 ns" { clk cnt4b[3] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 21.08 % ) " "Info: Total cell delay = 1.646 ns ( 21.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.162 ns ( 78.92 % ) " "Info: Total interconnect delay = 6.162 ns ( 78.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.490 ns" { ena cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.490 ns" { ena ena~out0 cnt4b[3] } { 0.000ns 0.000ns 5.154ns } { 0.000ns 1.469ns 0.867ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk50M freqa freqa~reg0 10.354 ns register " "Info: tco from clock \"clk50M\" to destination pin \"freqa\" through register \"freqa~reg0\" is 10.354 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk50M pll:u1\|altpll:altpll_component\|_clk0 -1.885 ns + " "Info: + Offset between input clock \"clk50M\" and output clock \"pll:u1\|altpll:altpll_component\|_clk0\" is -1.885 ns" { } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 7 -1 0 } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 source 7.808 ns + Longest register " "Info: + Longest clock path from clock \"pll:u1\|altpll:altpll_component\|_clk0\" to source register is 7.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 11; CLK Node = 'pll:u1\|altpll:altpll_component\|_clk0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.935 ns) 2.592 ns clk 2 REG LC_X16_Y10_N0 10 " "Info: 2: + IC(1.657 ns) + CELL(0.935 ns) = 2.592 ns; Loc. = LC_X16_Y10_N0; Fanout = 10; REG Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.592 ns" { pll:u1|altpll:altpll_component|_clk0 clk } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.505 ns) + CELL(0.711 ns) 7.808 ns freqa~reg0 3 REG LC_X1_Y8_N3 2 " "Info: 3: + IC(4.505 ns) + CELL(0.711 ns) = 7.808 ns; Loc. = LC_X1_Y8_N3; Fanout = 2; REG Node = 'freqa~reg0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.216 ns" { clk freqa~reg0 } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 65 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 21.08 % ) " "Info: Total cell delay = 1.646 ns ( 21.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.162 ns ( 78.92 % ) " "Info: Total interconnect delay = 6.162 ns ( 78.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk freqa~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk freqa~reg0 } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 65 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.207 ns + Longest register pin " "Info: + Longest register to pin delay is 4.207 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns freqa~reg0 1 REG LC_X1_Y8_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y8_N3; Fanout = 2; REG Node = 'freqa~reg0'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { freqa~reg0 } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 65 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.083 ns) + CELL(2.124 ns) 4.207 ns freqa 2 PIN PIN_23 0 " "Info: 2: + IC(2.083 ns) + CELL(2.124 ns) = 4.207 ns; Loc. = PIN_23; Fanout = 0; PIN Node = 'freqa'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.207 ns" { freqa~reg0 freqa } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 50.49 % ) " "Info: Total cell delay = 2.124 ns ( 50.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.083 ns ( 49.51 % ) " "Info: Total interconnect delay = 2.083 ns ( 49.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.207 ns" { freqa~reg0 freqa } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.207 ns" { freqa~reg0 freqa } { 0.000ns 2.083ns } { 0.000ns 2.124ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk freqa~reg0 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk freqa~reg0 } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.207 ns" { freqa~reg0 freqa } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.207 ns" { freqa~reg0 freqa } { 0.000ns 2.083ns } { 0.000ns 2.124ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "datab\[2\] b_data\[2\] updata 0.756 ns register " "Info: th for register \"datab\[2\]\" (data pin = \"b_data\[2\]\", clock pin = \"updata\") is 0.756 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "updata destination 6.887 ns + Longest register " "Info: + Longest clock path from clock \"updata\" to destination register is 6.887 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns updata 1 CLK PIN_38 8 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 8; CLK Node = 'updata'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { updata } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.707 ns) + CELL(0.711 ns) 6.887 ns datab\[2\] 2 REG LC_X1_Y7_N4 1 " "Info: 2: + IC(4.707 ns) + CELL(0.711 ns) = 6.887 ns; Loc. = LC_X1_Y7_N4; Fanout = 1; REG Node = 'datab\[2\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.418 ns" { updata datab[2] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 31.65 % ) " "Info: Total cell delay = 2.180 ns ( 31.65 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.707 ns ( 68.35 % ) " "Info: Total interconnect delay = 4.707 ns ( 68.35 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.887 ns" { updata datab[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.887 ns" { updata updata~out0 datab[2] } { 0.000ns 0.000ns 4.707ns } { 0.000ns 1.469ns 0.711ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 55 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.146 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.146 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns b_data\[2\] 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'b_data\[2\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { b_data[2] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.562 ns) + CELL(0.115 ns) 6.146 ns datab\[2\] 2 REG LC_X1_Y7_N4 1 " "Info: 2: + IC(4.562 ns) + CELL(0.115 ns) = 6.146 ns; Loc. = LC_X1_Y7_N4; Fanout = 1; REG Node = 'datab\[2\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.677 ns" { b_data[2] datab[2] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 55 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 25.77 % ) " "Info: Total cell delay = 1.584 ns ( 25.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.562 ns ( 74.23 % ) " "Info: Total interconnect delay = 4.562 ns ( 74.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.146 ns" { b_data[2] datab[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.146 ns" { b_data[2] b_data[2]~out0 datab[2] } { 0.000ns 0.000ns 4.562ns } { 0.000ns 1.469ns 0.115ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.887 ns" { updata datab[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.887 ns" { updata updata~out0 datab[2] } { 0.000ns 0.000ns 4.707ns } { 0.000ns 1.469ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.146 ns" { b_data[2] datab[2] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.146 ns" { b_data[2] b_data[2]~out0 datab[2] } { 0.000ns 0.000ns 4.562ns } { 0.000ns 1.469ns 0.115ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}
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