division.tan.qmsg

使用C8051F020和FPGA等其它相关硬件制作的一个程控滤波器

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk " "Info: Detected ripple clock \"clk\" as buffer" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 28 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 register cnt4b\[3\] register cnt4b\[0\] 16.649 ns " "Info: Slack time is 16.649 ns for clock \"pll:u1\|altpll:altpll_component\|_clk0\" between source register \"cnt4b\[3\]\" and destination register \"cnt4b\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.739 ns + Largest register register " "Info: + Largest register to register requirement is 19.739 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 18.115 ns " "Info: + Latch edge is 18.115 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:u1\|altpll:altpll_component\|_clk0 20.000 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"pll:u1\|altpll:altpll_component\|_clk0\" is 20.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:u1\|altpll:altpll_component\|_clk0 20.000 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pll:u1\|altpll:altpll_component\|_clk0\" is 20.000 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 destination 7.808 ns + Shortest register " "Info: + Shortest clock path from clock \"pll:u1\|altpll:altpll_component\|_clk0\" to destination register is 7.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 11; CLK Node = 'pll:u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.935 ns) 2.592 ns clk 2 REG LC_X16_Y10_N0 10 " "Info: 2: + IC(1.657 ns) + CELL(0.935 ns) = 2.592 ns; Loc. = LC_X16_Y10_N0; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.592 ns" { pll:u1|altpll:altpll_component|_clk0 clk } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.505 ns) + CELL(0.711 ns) 7.808 ns cnt4b\[0\] 3 REG LC_X1_Y7_N0 4 " "Info: 3: + IC(4.505 ns) + CELL(0.711 ns) = 7.808 ns; Loc. = LC_X1_Y7_N0; Fanout = 4; REG Node = 'cnt4b\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.216 ns" { clk cnt4b[0] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 21.08 % ) " "Info: Total cell delay = 1.646 ns ( 21.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.162 ns ( 78.92 % ) " "Info: Total interconnect delay = 6.162 ns ( 78.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:u1\|altpll:altpll_component\|_clk0 source 7.808 ns - Longest register " "Info: - Longest clock path from clock \"pll:u1\|altpll:altpll_component\|_clk0\" to source register is 7.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_2 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 11; CLK Node = 'pll:u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.657 ns) + CELL(0.935 ns) 2.592 ns clk 2 REG LC_X16_Y10_N0 10 " "Info: 2: + IC(1.657 ns) + CELL(0.935 ns) = 2.592 ns; Loc. = LC_X16_Y10_N0; Fanout = 10; REG Node = 'clk'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.592 ns" { pll:u1|altpll:altpll_component|_clk0 clk } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.505 ns) + CELL(0.711 ns) 7.808 ns cnt4b\[3\] 3 REG LC_X1_Y7_N2 3 " "Info: 3: + IC(4.505 ns) + CELL(0.711 ns) = 7.808 ns; Loc. = LC_X1_Y7_N2; Fanout = 3; REG Node = 'cnt4b\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.216 ns" { clk cnt4b[3] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns ( 21.08 % ) " "Info: Total cell delay = 1.646 ns ( 21.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.162 ns ( 78.92 % ) " "Info: Total interconnect delay = 6.162 ns ( 78.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.090 ns - Longest register register " "Info: - Longest register to register delay is 3.090 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt4b\[3\] 1 REG LC_X1_Y7_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y7_N2; Fanout = 3; REG Node = 'cnt4b\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt4b[3] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.145 ns) + CELL(0.442 ns) 1.587 ns Equal1~18 2 COMB LC_X1_Y8_N9 3 " "Info: 2: + IC(1.145 ns) + CELL(0.442 ns) = 1.587 ns; Loc. = LC_X1_Y8_N9; Fanout = 3; COMB Node = 'Equal1~18'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.587 ns" { cnt4b[3] Equal1~18 } "NODE_NAME" } } { "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/70/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(0.309 ns) 3.090 ns cnt4b\[0\] 3 REG LC_X1_Y7_N0 4 " "Info: 3: + IC(1.194 ns) + CELL(0.309 ns) = 3.090 ns; Loc. = LC_X1_Y7_N0; Fanout = 4; REG Node = 'cnt4b\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.503 ns" { Equal1~18 cnt4b[0] } "NODE_NAME" } } { "division.vhd" "" { Text "E:/滤波器/数控分频器FPGA/division.vhd" 83 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.751 ns ( 24.30 % ) " "Info: Total cell delay = 0.751 ns ( 24.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.339 ns ( 75.70 % ) " "Info: Total interconnect delay = 2.339 ns ( 75.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { cnt4b[3] Equal1~18 cnt4b[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.090 ns" { cnt4b[3] Equal1~18 cnt4b[0] } { 0.000ns 1.145ns 1.194ns } { 0.000ns 0.442ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[0] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.808 ns" { pll:u1|altpll:altpll_component|_clk0 clk cnt4b[3] } { 0.000ns 1.657ns 4.505ns } { 0.000ns 0.935ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.090 ns" { cnt4b[3] Equal1~18 cnt4b[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.090 ns" { cnt4b[3] Equal1~18 cnt4b[0] } { 0.000ns 1.145ns 1.194ns } { 0.000ns 0.442ns 0.309ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk50M " "Info: No valid register-to-register data paths exist for clock \"clk50M\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "updata " "Info: No valid register-to-register data paths exist for clock \"updata\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}