sin.vhd

使用C8051F020和FPGA设计的低频信号相位测量仪器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY SIN IS                                   -------- 顶层设计
 PORT ( --------移相正弦信号 
         CLKIN_12M : IN  STD_LOGIC;         
         WORD      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);     --用于赋值给频率控制字和相位控制字
         RESET     : IN  STD_LOGIC;            --复位
         W_CLK     : IN  STD_LOGIC;            --数据更新时钟
         UPWORD    : IN  STD_LOGIC;            --数据更新
         FOUT      : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
         POUT      : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); 

       -----------测试频率
         BCLK	 : IN	STD_LOGIC;        --基准频率
		 SCLK0   : IN   STD_LOGIC;        --整形后第1路正弦信号
		 SCLK1   : IN   STD_LOGIC;        --整形后第2路正弦信号
		 CLR 	 : IN	STD_LOGIC;        --清零
		 ENA     : IN	STD_LOGIC;        --预置门控信号，用于测频计数时间的控制
		 SEL     : IN   STD_LOGIC_VECTOR(3 DOWNTO 0);   --数据读出选择控制
		 READ    : IN   STD_LOGIC;
		 DATA    : OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);  --8位数据读出
		 QOUT    : OUT  STD_LOGIC        --相位极性判断输出 
		);
 END;

ARCHITECTURE one OF SIN IS
    TYPE STATES IS (S0,S1,S2,S3);
    SIGNAL STATE : STATES;

    COMPONENT REG24B                                      --24位寄存器
        PORT (  LOAD : IN STD_LOGIC;
                 DIN : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) );
    END COMPONENT;

    COMPONENT REG10B                                      --10位寄存器
        PORT (  LOAD :  IN STD_LOGIC;
                 DIN :  IN STD_LOGIC_VECTOR(9 DOWNTO 0);
                DOUT : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) );
    END COMPONENT;

    COMPONENT ADDER24B                                    --24位累加器
       PORT (  A : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
               B : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)     );
    END COMPONENT;

    COMPONENT ADDER10B                                   --10位累加器
       PORT (  A : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
               B : IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)     );
    END COMPONENT;

    COMPONENT SIN_ROM                                    --正弦ROM生成表
      PORT	( address	: IN STD_LOGIC_VECTOR(9 DOWNTO 0);
		      inclock	: IN STD_LOGIC ;
	            	q	: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)	);
    END COMPONENT; 
                                                   ---移相正弦信号中间信号的使用
     SIGNAL FWORD  : STD_LOGIC_VECTOR(15 DOWNTO 0);
     SIGNAL PWORD  : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL F24B   : STD_LOGIC_VECTOR(23 DOWNTO 0);
     SIGNAL D24B   : STD_LOGIC_VECTOR(23 DOWNTO 0);
     SIGNAL DIN24B : STD_LOGIC_VECTOR(23 DOWNTO 0);
     SIGNAL P10B   : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL LIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL SIN10B : STD_LOGIC_VECTOR( 9 DOWNTO 0);
     SIGNAL CLK_6M :STD_LOGIC;
                                                    ---测频率中间信号的使用
     SIGNAL  TCLK: STD_LOGIC;
	 SIGNAL	 BZQ : STD_LOGIC_VECTOR(31 DOWNTO 0);    --标准计数器
     SIGNAL  TSQ : STD_LOGIC_VECTOR(31 DOWNTO 0);    --测频计数器
	 SIGNAL  SQ  : STD_LOGIC_VECTOR(15 DOWNTO 0);
	 SIGNAL  DATA0 : STD_LOGIC_VECTOR(7 DOWNTO 0);
	 
    
BEGIN                       
                                  ----------------------测试频率
TCLK <= (SCLK0 XOR SCLK1) AND BCLK;                   --两路放大整形的相位差信号,异或后和基准频率信号相与
     
SEL_WORD : PROCESS (SEL,ENA)
             BEGIN
              IF RISING_EDGE(READ) THEN                         
                  CASE SEL IS 
                   WHEN "0000" =>DATA<=BZQ(31 DOWNTO 24);      --标准频率计数高8位输出
                   WHEN "0001" =>DATA<=BZQ(23 DOWNTO 16);
                   WHEN "0010" =>DATA<=BZQ(15 DOWNTO 8 );
                   WHEN "0011" =>DATA<=BZQ(7  DOWNTO 0 ); 
                   WHEN "0100" =>DATA<=TSQ(31 DOWNTO 24);      --待测频率TCLK计数高8位输出
	               WHEN "0101" =>DATA<=TSQ(23 DOWNTO 16);  
	               WHEN "0110" =>DATA<=TSQ(15 DOWNTO 8 ); 
	               WHEN "0111" =>DATA<=TSQ( 7 DOWNTO 0 );
	               WHEN "1000" =>DATA<=SQ (15 DOWNTO 8 );      --待测频率SCLK0/1计数高8位输出
	               WHEN "1001" =>DATA<=SQ ( 7 DOWNTO 0 );
	               WHEN OTHERS =>DATA<=(OTHERS=>'0'); 
	              END CASE;	       
	          END IF;
           END PROCESS;
BZH : PROCESS (BCLK,CLR,ENA)                             --基准频率测试计数器          
       BEGIN 
         IF CLR = '1' THEN BZQ <= (OTHERS=>'0');         --CLR=1清零
         ELSIF  ENA = '1' THEN 
            IF BCLK'EVENT AND BCLK = '1' THEN 
               BZQ <=BZQ+1;
            END IF;
         END IF;
      END PROCESS;
TF  : PROCESS (TCLK,CLR,ENA)                             --TCLK频率测试计数器       
        BEGIN 
           IF CLR = '1' THEN TSQ <= (OTHERS=>'0');       
            ELSIF ENA = '1' THEN
               IF TCLK'EVENT AND TCLK = '1' THEN 
                  TSQ <=TSQ + 1;
               END IF;
           END IF;
      END PROCESS;
SF  : PROCESS (SCLK0,CLR,ENA)                            --SCLK0频率测试计数器
        BEGIN 
           IF CLR = '1' THEN  SQ <= (OTHERS=>'0');       
            ELSIF ENA = '1' THEN
               IF SCLK0'EVENT AND SCLK0 = '1' THEN 
                  SQ <=SQ + 1;
               END IF;
           END IF;
      END PROCESS;
Polatiry : PROCESS(SCLK1)                       --相位极性判别
             BEGIN                                    --SCLK0超前SCLK1,QOUT输出高电平
               IF RISING_EDGE(SCLK1) THEN             --SCLK0滞后SCLK1,QOUT输出低电平
                  QOUT<=SCLK0;
               END IF;
           END PROCESS;
 

                                       ------------------移相正弦信号
DivClk: PROCESS(CLKIN_12M)
          BEGIN
           IF RISING_EDGE(CLKIN_12M) THEN
              CLK_6M<= NOT CLK_6M;
           END IF;
        END PROCESS;

-------"0000000000111000"

WORD_CHANGE:PROCESS(WORD,UPWORD)
              BEGIN
              IF RESET = '0' THEN
                 IF UPWORD='0' THEN  
                   IF RISING_EDGE(W_CLK) THEN
                   CASE STATE IS 
                   WHEN S0=> FWORD(15 DOWNTO 8)<=WORD; STATE<=S1;      --频率控制字高8位输入
                   WHEN S1=> FWORD(7 DOWNTO 0) <=WORD; STATE<=S2;      
                   WHEN S2=> PWORD(9 DOWNTO 8) <=WORD(1 DOWNTO 0); STATE<=S3;  --相位控制字高2位输入
                   WHEN S3=> PWORD(7 DOWNTO 0) <=WORD;STATE<=S0;       --相位控制字低8位输入
                   WHEN OTHERS => STATE<=S0;
                   END CASE;
                   END IF;
                 ELSIF RISING_EDGE(UPWORD) THEN                          
                   F24B(15 DOWNTO 0)<=FWORD ;              --频率控制字给24位累加器
                   F24B(23 DOWNTO 16)<="00000000" ;       
                   P10B<=PWORD ;                           --相位控制字给10位累加器      
                 END IF;
              ELSE 
                  STATE<=S0;
                  FWORD<="0000000000000000";
                  PWORD<="0000000000";
              END IF;
      END PROCESS; 

 u1 : ADDER24B  PORT MAP( A=>F24B,B=>D24B, S=>DIN24B );
 u2 :   REG24B  PORT MAP( DOUT=>D24B,DIN=> DIN24B, LOAD=>CLK_6M );
 u3 :  SIN_ROM  PORT MAP( address=>SIN10B, q=>FOUT, inclock=>CLK_6M );
 u4 : ADDER10B  PORT MAP( A=>P10B,B=>D24B(23 DOWNTO 14),S=>LIN10B );
 u5 :   REG10B  PORT MAP( DOUT=>SIN10B,DIN=>LIN10B, LOAD=>CLK_6M );
 u6 : SIN_ROM   PORT MAP(address=>D24B(23 downto 14),q=>POUT,inclock=>CLK_6M); 
END;